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sp_sm2_arm32.c
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sp_sm2_arm32.c
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/* sp.c
*
* Copyright (C) 2006-2023 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/* Implementation by Sean Parkinson. */
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <wolfssl/wolfcrypt/settings.h>
#if defined(WOLFSSL_HAVE_SP_RSA) || defined(WOLFSSL_HAVE_SP_DH) || \
defined(WOLFSSL_HAVE_SP_ECC)
#include <wolfssl/wolfcrypt/error-crypt.h>
#include <wolfssl/wolfcrypt/cpuid.h>
#ifdef NO_INLINE
#include <wolfssl/wolfcrypt/misc.h>
#else
#define WOLFSSL_MISC_INCLUDED
#include <wolfcrypt/src/misc.c>
#endif
#ifdef RSA_LOW_MEM
#ifndef WOLFSSL_SP_SMALL
#define WOLFSSL_SP_SMALL
#endif
#endif
#if defined(WOLFSSL_SMALL_STACK) && !defined(WOLFSSL_SP_NO_MALLOC)
#undef WOLFSSL_SP_SMALL_STACK
#define WOLFSSL_SP_SMALL_STACK
#endif
#include <wolfssl/wolfcrypt/sp.h>
#ifdef __IAR_SYSTEMS_ICC__
#define __asm__ asm
#define __volatile__ volatile
#endif /* __IAR_SYSTEMS_ICC__ */
#ifdef __KEIL__
#define __asm__ __asm
#define __volatile__ volatile
#endif
#ifdef WOLFSSL_SP_ARM32_ASM
#define SP_PRINT_NUM(var, name, total, words, bits) \
do { \
int ii; \
fprintf(stderr, name "=0x"); \
for (ii = ((bits + 31) / 32) - 1; ii >= 0; ii--) \
fprintf(stderr, SP_PRINT_FMT, (var)[ii]); \
fprintf(stderr, "\n"); \
} while (0)
#define SP_PRINT_VAL(var, name) \
fprintf(stderr, name "=0x" SP_PRINT_FMT "\n", var)
#define SP_PRINT_INT(var, name) \
fprintf(stderr, name "=%d\n", var)
#ifdef WOLFSSL_HAVE_SP_ECC
#ifdef WOLFSSL_SP_SM2
/* Point structure to use. */
typedef struct sp_point_256 {
/* X ordinate of point. */
sp_digit x[2 * 8];
/* Y ordinate of point. */
sp_digit y[2 * 8];
/* Z ordinate of point. */
sp_digit z[2 * 8];
/* Indicates point is at infinity. */
int infinity;
} sp_point_256;
/* The modulus (prime) of the curve SM2 P256. */
static const sp_digit p256_sm2_mod[8] = {
0xffffffff,0xffffffff,0x00000000,0xffffffff,0xffffffff,0xffffffff,
0xffffffff,0xfffffffe
};
/* The Montgomery normalizer for modulus of the curve P256. */
static const sp_digit p256_sm2_norm_mod[8] = {
0x00000001,0x00000000,0xffffffff,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000001
};
/* The Montgomery multiplier for modulus of the curve P256. */
static const sp_digit p256_sm2_mp_mod = 0x00000001;
#if defined(WOLFSSL_VALIDATE_ECC_KEYGEN) || defined(HAVE_ECC_SIGN) || \
defined(HAVE_ECC_VERIFY)
/* The order of the curve P256. */
static const sp_digit p256_sm2_order[8] = {
0x39d54123,0x53bbf409,0x21c6052b,0x7203df6b,0xffffffff,0xffffffff,
0xffffffff,0xfffffffe
};
#endif
/* The order of the curve P256 minus 2. */
static const sp_digit p256_sm2_order2[8] = {
0x39d54121,0x53bbf409,0x21c6052b,0x7203df6b,0xffffffff,0xffffffff,
0xffffffff,0xfffffffe
};
#if defined(HAVE_ECC_SIGN)
/* The Montgomery normalizer for order of the curve P256. */
static const sp_digit p256_sm2_norm_order[8] = {
0xc62abedd,0xac440bf6,0xde39fad4,0x8dfc2094,0x00000000,0x00000000,
0x00000000,0x00000001
};
#endif
#if defined(HAVE_ECC_SIGN)
/* The Montgomery multiplier for order of the curve P256. */
static const sp_digit p256_sm2_mp_order = 0x72350975;
#endif
/* The base point of curve P256. */
static const sp_point_256 p256_sm2_base = {
/* X ordinate */
{
0x334c74c7,0x715a4589,0xf2660be1,0x8fe30bbf,0x6a39c994,0x5f990446,
0x1f198119,0x32c4ae2c,
(sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0,
(sp_digit)0, (sp_digit)0, (sp_digit)0
},
/* Y ordinate */
{
0x2139f0a0,0x02df32e5,0xc62a4740,0xd0a9877c,0x6b692153,0x59bdcee3,
0xf4f6779c,0xbc3736a2,
(sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0,
(sp_digit)0, (sp_digit)0, (sp_digit)0
},
/* Z ordinate */
{
0x00000001,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
(sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0, (sp_digit)0,
(sp_digit)0, (sp_digit)0, (sp_digit)0
},
/* infinity */
0
};
#if defined(HAVE_ECC_CHECK_KEY) || defined(HAVE_COMP_KEY)
static const sp_digit p256_sm2_b[8] = {
0x4d940e93,0xddbcbd41,0x15ab8f92,0xf39789f5,0xcf6509a7,0x4d5a9e4b,
0x9d9f5e34,0x28e9fa9e
};
#endif
#ifdef WOLFSSL_SP_SMALL
/* Multiply a and b into r. (r = a * b)
*
* r A single precision integer.
* a A single precision integer.
* b A single precision integer.
*/
static void sp_256_mul_sm2_8(sp_digit* r_p, const sp_digit* a_p, const sp_digit* b_p)
{
register sp_digit* r asm ("r0") = (sp_digit*)r_p;
register const sp_digit* a asm ("r1") = (const sp_digit*)a_p;
register const sp_digit* b asm ("r2") = (const sp_digit*)b_p;
__asm__ __volatile__ (
"sub sp, sp, #0x40\n\t"
"mov r5, #0\n\t"
"mov r6, #0\n\t"
"mov r7, #0\n\t"
"mov r8, #0\n\t"
"\n"
"L_sp_256_mul_sm2_8_outer_%=: \n\t"
"subs r3, r5, #28\n\t"
"it cc\n\t"
"movcc r3, #0\n\t"
"sub r4, r5, r3\n\t"
"\n"
"L_sp_256_mul_sm2_8_inner_%=: \n\t"
"ldr lr, [%[a], r3]\n\t"
"ldr r11, [%[b], r4]\n\t"
#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 4)
"lsl r9, lr, #16\n\t"
"lsl r10, r11, #16\n\t"
"lsr r9, r9, #16\n\t"
"lsr r10, r10, #16\n\t"
"mul r10, r9, r10\n\t"
"adds r6, r6, r10\n\t"
"adcs r7, r7, #0\n\t"
"adc r8, r8, #0\n\t"
"lsr r10, r11, #16\n\t"
"mul r9, r10, r9\n\t"
"lsr r10, r9, #16\n\t"
"lsl r9, r9, #16\n\t"
"adds r6, r6, r9\n\t"
"adcs r7, r7, r10\n\t"
"adc r8, r8, #0\n\t"
"lsr r9, lr, #16\n\t"
"lsr r10, r11, #16\n\t"
"mul r10, r9, r10\n\t"
"adds r7, r7, r10\n\t"
"adc r8, r8, #0\n\t"
"lsl r10, r11, #16\n\t"
"lsr r10, r10, #16\n\t"
"mul r9, r10, r9\n\t"
"lsr r10, r9, #16\n\t"
"lsl r9, r9, #16\n\t"
"adds r6, r6, r9\n\t"
"adcs r7, r7, r10\n\t"
"adc r8, r8, #0\n\t"
#else
"umull r9, r10, lr, r11\n\t"
"adds r6, r6, r9\n\t"
"adcs r7, r7, r10\n\t"
"adc r8, r8, #0\n\t"
#endif
"add r3, r3, #4\n\t"
"sub r4, r4, #4\n\t"
"cmp r3, #32\n\t"
"beq L_sp_256_mul_sm2_8_inner_done_%=\n\t"
"cmp r3, r5\n\t"
"ble L_sp_256_mul_sm2_8_inner_%=\n\t"
"\n"
"L_sp_256_mul_sm2_8_inner_done_%=: \n\t"
"str r6, [sp, r5]\n\t"
"mov r6, r7\n\t"
"mov r7, r8\n\t"
"mov r8, #0\n\t"
"add r5, r5, #4\n\t"
"cmp r5, #56\n\t"
"ble L_sp_256_mul_sm2_8_outer_%=\n\t"
"str r6, [sp, r5]\n\t"
"\n"
"L_sp_256_mul_sm2_8_store_%=: \n\t"
"ldm sp!, {r6, r7, r8, r9}\n\t"
"stm %[r]!, {r6, r7, r8, r9}\n\t"
"subs r5, r5, #16\n\t"
"bgt L_sp_256_mul_sm2_8_store_%=\n\t"
: [r] "+r" (r), [a] "+r" (a), [b] "+r" (b)
:
: "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "lr", "r11"
);
}
#else
#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 4)
/* Multiply a and b into r. (r = a * b)
*
* r A single precision integer.
* a A single precision integer.
* b A single precision integer.
*/
static void sp_256_mul_sm2_8(sp_digit* r_p, const sp_digit* a_p, const sp_digit* b_p)
{
register sp_digit* r asm ("r0") = (sp_digit*)r_p;
register const sp_digit* a asm ("r1") = (const sp_digit*)a_p;
register const sp_digit* b asm ("r2") = (const sp_digit*)b_p;
__asm__ __volatile__ (
"sub sp, sp, #32\n\t"
/* A[0] * B[0] */
"ldr r11, [%[a]]\n\t"
"ldr r12, [%[b]]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r3, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r3, r3, #16\n\t"
"mul r3, r6, r3\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r4, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r11, #16\n\t"
"mul r7, r6, r7\n\t"
"add r4, r4, r7\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adc r4, r4, r7\n\t"
"mov r5, #0\n\t"
"str r3, [sp]\n\t"
/* A[0] * B[1] */
"ldr r9, [%[b], #4]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"mov r3, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r11, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
/* A[1] * B[0] */
"ldr r8, [%[a], #4]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"str r4, [sp, #4]\n\t"
/* A[2] * B[0] */
"ldr r8, [%[a], #8]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"mov r4, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[1] * B[1] */
"ldr r11, [%[a], #4]\n\t"
"ldr r12, [%[b], #4]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r11, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[0] * B[2] */
"ldr r8, [%[a]]\n\t"
"ldr r9, [%[b], #8]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"str r5, [sp, #8]\n\t"
/* A[0] * B[3] */
"ldr r9, [%[b], #12]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"mov r5, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
/* A[1] * B[2] */
"ldr r9, [%[b], #8]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r11, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
/* A[2] * B[1] */
"ldr r8, [%[a], #8]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
/* A[3] * B[0] */
"ldr r8, [%[a], #12]\n\t"
"ldr r9, [%[b]]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"str r3, [sp, #12]\n\t"
/* A[4] * B[0] */
"ldr r8, [%[a], #16]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"mov r3, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
/* A[3] * B[1] */
"ldr r8, [%[a], #12]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
/* A[2] * B[2] */
"ldr r11, [%[a], #8]\n\t"
"ldr r12, [%[b], #8]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r11, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
/* A[1] * B[3] */
"ldr r8, [%[a], #4]\n\t"
"ldr r9, [%[b], #12]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
/* A[0] * B[4] */
"ldr r8, [%[a]]\n\t"
"ldr r9, [%[b], #16]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adcs r5, r5, #0\n\t"
"adc r3, r3, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r4, r4, r6\n\t"
"adcs r5, r5, r7\n\t"
"adc r3, r3, #0\n\t"
"str r4, [sp, #16]\n\t"
/* A[0] * B[5] */
"ldr r9, [%[b], #20]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"mov r4, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[1] * B[4] */
"ldr r8, [%[a], #4]\n\t"
"ldr r9, [%[b], #16]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[2] * B[3] */
"ldr r9, [%[b], #12]\n\t"
"lsl r6, r11, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r11, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[3] * B[2] */
"ldr r8, [%[a], #12]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r12, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[4] * B[1] */
"ldr r8, [%[a], #16]\n\t"
"ldr r9, [%[b], #4]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
/* A[5] * B[0] */
"ldr r8, [%[a], #20]\n\t"
"ldr r9, [%[b]]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r5, r5, r7\n\t"
"adcs r3, r3, #0\n\t"
"adc r4, r4, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r5, r5, r6\n\t"
"adcs r3, r3, r7\n\t"
"adc r4, r4, #0\n\t"
"str r5, [sp, #20]\n\t"
/* A[6] * B[0] */
"ldr r8, [%[a], #24]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"mov r5, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
/* A[5] * B[1] */
"ldr r8, [%[a], #20]\n\t"
"ldr r9, [%[b], #4]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r9, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r9, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r9, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsl r7, r9, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
/* A[4] * B[2] */
"ldr r8, [%[a], #16]\n\t"
"lsl r6, r8, #16\n\t"
"lsl r7, r12, #16\n\t"
"lsr r6, r6, #16\n\t"
"lsr r7, r7, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r3, r3, r7\n\t"
"adcs r4, r4, #0\n\t"
"adc r5, r5, #0\n\t"
"lsr r7, r12, #16\n\t"
"mul r6, r7, r6\n\t"
"lsr r7, r6, #16\n\t"
"lsl r6, r6, #16\n\t"
"adds r3, r3, r6\n\t"
"adcs r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"
"lsr r6, r8, #16\n\t"
"lsr r7, r12, #16\n\t"
"mul r7, r6, r7\n\t"
"adds r4, r4, r7\n\t"
"adc r5, r5, #0\n\t"