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mir-gen-riscv64.c
2841 lines (2646 loc) · 118 KB
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mir-gen-riscv64.c
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/* This file is a part of MIR project.
Copyright (C) 2020-2023 Vladimir Makarov <vmakarov.gcc@gmail.com>.
*/
/* In MIR generated code unsigned 32-bit values are zero extended but
passing/returning such value is signed extended (which is their
riscv ABI representation).
In theory we should pass vararg unsigned as sign extended according
to ABI but gcc/clang va_arg code do the correct sign extension
anyway. So we can ignore sign extension for integer vararg
arguments. */
/* ??? TODO: o compressed c.j, c.beqz, c.bnez (is it worth because such jumps are
usually forward and it requires complicated algorithm for relaxing)
o rd = rs - const -> rd = rs + (-const) for using addi
o implement generation for FLEN=128
o save/set/restore sp/fp only we use it
o optimization: remove ext32 for branches generated in machinize if operands
are generated by short insns
*/
static void fancy_abort (int code) {
if (!code) abort ();
}
#undef gen_assert
#define gen_assert(c) fancy_abort (c)
#include <limits.h>
#define HREG_EL(h) h##_HARD_REG
#define REP_SEP ,
enum {
REP8 (HREG_EL, R0, R1, R2, R3, R4, R5, R6, R7),
REP8 (HREG_EL, R8, R9, R10, R11, R12, R13, R14, R15),
REP8 (HREG_EL, R16, R17, R18, R19, R20, R21, R22, R23),
REP8 (HREG_EL, R24, R25, R26, R27, R28, R29, R30, R31),
/*Aliases: */ ZERO_HARD_REG = R0_HARD_REG,
REP7 (HREG_EL, RA, SP, GP, TP, T0, T1, T2),
REP8 (HREG_EL, FP, S1, A0, A1, A2, A3, A4, A5),
REP8 (HREG_EL, A6, A7, S2, S3, S4, S5, S6, S7),
REP8 (HREG_EL, S8, S9, S10, S11, T3, T4, T5, T6),
REP8 (HREG_EL, F0, F1, F2, F3, F4, F5, F6, F7),
REP8 (HREG_EL, F8, F9, F10, F11, F12, F13, F14, F15),
REP8 (HREG_EL, F16, F17, F18, F19, F20, F21, F22, F23),
REP8 (HREG_EL, F24, F25, F26, F27, F28, F29, F30, F31),
/* Aliases: */ FT0_HARD_REG = F0_HARD_REG,
REP7 (HREG_EL, FT1, FT2, FT3, FT4, FT5, FT6, FT7),
REP8 (HREG_EL, FS0, FS1, FA0, FA1, FA2, FA3, FA4, FA5),
REP8 (HREG_EL, FA6, FA7, FS2, FS3, FS4, FS5, FS6, FS7),
REP8 (HREG_EL, FS8, FS9, FS10, FS11, FT8, FT9, FT10, FT11),
};
static const MIR_reg_t hard_reg_alloc_order[] = {
REP8 (HREG_EL, R8, R9, R10, R11, R12, R13, R14, R15),
REP8 (HREG_EL, F8, F9, F10, F11, F12, F13, F14, F15),
REP8 (HREG_EL, R0, R1, R2, R3, R4, R5, R6, R7),
REP8 (HREG_EL, R16, R17, R18, R19, R20, R21, R22, R23),
REP8 (HREG_EL, R24, R25, R26, R27, R28, R29, R30, R31),
REP8 (HREG_EL, F0, F1, F2, F3, F4, F5, F6, F7),
REP8 (HREG_EL, F16, F17, F18, F19, F20, F21, F22, F23),
REP8 (HREG_EL, F24, F25, F26, F27, F28, F29, F30, F31),
};
#undef REP_SEP
static const MIR_reg_t MAX_HARD_REG = F31_HARD_REG;
static const MIR_reg_t LINK_HARD_REG = RA_HARD_REG;
#define TARGET_HARD_REG_ALLOC_ORDER(n) hard_reg_alloc_order[n]
static void check_hard_reg_alloc_order (void) {
int i;
char check_p[F31_HARD_REG + 1];
gen_assert (MAX_HARD_REG == F31_HARD_REG
&& sizeof (hard_reg_alloc_order) / sizeof (MIR_reg_t) == MAX_HARD_REG + 1);
for (i = 0; i <= MAX_HARD_REG; i++) check_p[i] = FALSE;
for (i = 0; i <= MAX_HARD_REG; i++) {
gen_assert (!check_p[hard_reg_alloc_order[i]]);
check_p[hard_reg_alloc_order[i]] = TRUE;
}
for (i = 0; i <= MAX_HARD_REG; i++) gen_assert (check_p[i]);
}
static int target_locs_num (MIR_reg_t loc, MIR_type_t type) {
return loc > MAX_HARD_REG && type == MIR_T_LD ? 2 : 1;
}
static inline MIR_reg_t target_nth_loc (MIR_reg_t loc, MIR_type_t type, int n) { return loc + n; }
/* Hard regs not used in machinized code, preferably call used ones. */
const MIR_reg_t TEMP_INT_HARD_REG1 = T5_HARD_REG, TEMP_INT_HARD_REG2 = T6_HARD_REG;
const MIR_reg_t TEMP_FLOAT_HARD_REG1 = FT10_HARD_REG, TEMP_FLOAT_HARD_REG2 = FT11_HARD_REG;
const MIR_reg_t TEMP_DOUBLE_HARD_REG1 = FT10_HARD_REG, TEMP_DOUBLE_HARD_REG2 = FT11_HARD_REG;
/* we use only builtins for long double ops: */
const MIR_reg_t TEMP_LDOUBLE_HARD_REG1 = MIR_NON_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG2 = MIR_NON_HARD_REG;
static inline int target_hard_reg_type_ok_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
if (type == MIR_T_LD) return FALSE; /* long double can be in hard regs only for arg passing */
return MIR_fp_type_p (type) ? hard_reg >= F0_HARD_REG : hard_reg < F0_HARD_REG;
}
static inline int target_fixed_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return (hard_reg == ZERO_HARD_REG || hard_reg == FP_HARD_REG || hard_reg == SP_HARD_REG
|| hard_reg == GP_HARD_REG || hard_reg == TP_HARD_REG // ???
|| hard_reg == TEMP_INT_HARD_REG1 || hard_reg == TEMP_INT_HARD_REG2
|| hard_reg == TEMP_FLOAT_HARD_REG1 || hard_reg == TEMP_FLOAT_HARD_REG2
|| hard_reg == TEMP_DOUBLE_HARD_REG1 || hard_reg == TEMP_DOUBLE_HARD_REG2
|| hard_reg == TEMP_LDOUBLE_HARD_REG1 || hard_reg == TEMP_LDOUBLE_HARD_REG2);
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
if (hard_reg <= R31_HARD_REG)
return !(hard_reg == R8_HARD_REG || hard_reg == R9_HARD_REG
|| (hard_reg >= R18_HARD_REG && hard_reg <= R27_HARD_REG));
return type == MIR_T_LD
|| !(hard_reg == F8_HARD_REG || hard_reg == F9_HARD_REG
|| (hard_reg >= F18_HARD_REG && hard_reg <= F27_HARD_REG));
}
/* Stack layout (sp refers to the last reserved stack slot address)
from higher address to lower address memory:
| ... | prev func stack (start aligned to 16 bytes)
|---------------|
| gr save area | optional area for vararg func reg save area
| | (int arg regs corresponding to varargs)
|---------------|
| saved regs | callee saved regs used in the func (known only after RA), rounded 16 bytes
|---------------|
| slots assigned| can be absent for small functions (known only after RA), rounded 16 bytes
| to pseudos |
|---------------|
| previous | (sp right after call) 16-bytes setup in prolog, used only for varag func or
| stack start | args passed on stack to move args and to setup va_start on machinize pass
|---------------|
| RA | sp before prologue and after saving RA = start sp
|---------------|
| old FP | frame pointer for previous func stack frame; new FP refers for here
|---------------|
| small aggreg |
| save area | optional
|---------------|
| alloca areas | optional
|---------------|
| slots for | dynamically allocated/deallocated by caller
| passing args |
size of slots and saved regs is multiple of 16 bytes
*/
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {MIR_INSN_BOUND};
/* Return extension insn for passing args and returns. */
static MIR_insn_code_t get_ext_code (MIR_type_t type, int arg_pass_p) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32:
/* even unsigned 32-bit is extended by sign according to ABI -- pass it the right way: */
return (arg_pass_p ? MIR_EXT32 : MIR_UEXT32);
default: return MIR_INVALID_INSN;
}
}
static MIR_reg_t get_arg_reg (MIR_type_t arg_type, int vararg_p, size_t *int_arg_num,
size_t *fp_arg_num, MIR_insn_code_t *mov_code) {
MIR_reg_t arg_reg;
if (!vararg_p && (arg_type == MIR_T_F || arg_type == MIR_T_D)) {
switch (*fp_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = FA0_HARD_REG + *fp_arg_num; break;
default: arg_reg = MIR_NON_HARD_REG; break;
}
(*fp_arg_num)++;
*mov_code = arg_type == MIR_T_F ? MIR_FMOV : MIR_DMOV;
} else { /* including LD, BLK, RBLK: */
if (arg_type == MIR_T_LD && *int_arg_num % 2 != 0) (*int_arg_num)++;
switch (*int_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = A0_HARD_REG + *int_arg_num; break;
default: arg_reg = MIR_NON_HARD_REG; break;
}
(*int_arg_num)++;
if (arg_type != MIR_T_LD) {
*mov_code = MIR_MOV;
} else {
(*int_arg_num)++;
*mov_code = MIR_LDMOV;
}
}
return arg_reg;
}
static void mir_blk_mov (uint64_t *to, uint64_t *from, uint64_t nwords) {
for (; nwords > 0; nwords--) *to++ = *from++;
}
static MIR_insn_t gen_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_insn_code_t code,
MIR_op_t dst_op, MIR_op_t src_op) {
MIR_insn_t insn = MIR_new_insn (gen_ctx->ctx, code, dst_op, src_op);
gen_add_insn_before (gen_ctx, anchor, insn);
return insn;
}
static const char *BLK_MOV = "mir.blk_mov";
static const char *BLK_MOV_P = "mir.blk_mov.p";
static void gen_blk_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, size_t to_disp,
MIR_reg_t to_base_hard_reg, MIR_reg_t from_base_reg, size_t qwords,
int save_regs) {
size_t from_disp = 0;
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_item_t proto_item, func_import_item;
MIR_insn_t new_insn;
MIR_op_t ops[5], freg_op, treg_op, treg_op2, treg_op3, treg_op4;
treg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
treg_op2 = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
if (qwords <= 16) {
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op2, MIR_new_int_op (ctx, to_disp));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, treg_op2, treg_op2,
_MIR_new_hard_reg_op (ctx, to_base_hard_reg)));
for (; qwords > 0; qwords--, to_disp += 8, from_disp += 8) {
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op,
MIR_new_mem_op (ctx, MIR_T_I64, from_disp, from_base_reg, 0, 1));
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, to_disp, to_base_hard_reg,
MIR_NON_HARD_REG, 1),
treg_op);
}
return;
}
treg_op3 = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
/* Save arg regs: */
if (save_regs > 0)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op, _MIR_new_hard_reg_op (ctx, A0_HARD_REG));
if (save_regs > 1)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op2, _MIR_new_hard_reg_op (ctx, A1_HARD_REG));
if (save_regs > 2)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op3, _MIR_new_hard_reg_op (ctx, A2_HARD_REG));
/* call blk move: */
proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, BLK_MOV_P, 0, NULL, 3, MIR_T_I64,
"to", MIR_T_I64, "from", MIR_T_I64, "nwords");
func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, BLK_MOV, mir_blk_mov);
freg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, anchor, new_insn);
treg_op4 = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op4, MIR_new_int_op (ctx, to_disp));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, A0_HARD_REG),
_MIR_new_hard_reg_op (ctx, to_base_hard_reg), treg_op4));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, A1_HARD_REG),
MIR_new_reg_op (ctx, from_base_reg),
MIR_new_int_op (ctx, from_disp)));
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, A2_HARD_REG),
MIR_new_int_op (ctx, qwords));
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = _MIR_new_hard_reg_op (ctx, A0_HARD_REG);
ops[3] = _MIR_new_hard_reg_op (ctx, A1_HARD_REG);
ops[4] = _MIR_new_hard_reg_op (ctx, A2_HARD_REG);
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_before (gen_ctx, anchor, new_insn);
/* Restore arg regs: */
if (save_regs > 0)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, A0_HARD_REG), treg_op);
if (save_regs > 1)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, A1_HARD_REG), treg_op2);
if (save_regs > 2)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, R2_HARD_REG), treg_op3);
}
#define FMVXW_CODE 0
#define FMVXD_CODE 1
static void machinize_call (gen_ctx_t gen_ctx, MIR_insn_t call_insn) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
int float_p;
size_t nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t int_arg_num = 0, fp_arg_num = 0, mem_size = 0, blk_offset = 0, qwords;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t arg_reg;
MIR_op_t arg_op, temp_op, arg_reg_op, ret_reg_op, mem_op, treg_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, prev_insn, next_insn, ext_insn;
MIR_insn_t prev_call_insn = DLIST_PREV (MIR_insn_t, call_insn);
MIR_insn_t curr_prev_call_insn = prev_call_insn;
assert (__SIZEOF_LONG_DOUBLE__ == 16);
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (proto->vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
if (call_insn->ops[1].mode != MIR_OP_REG && call_insn->ops[1].mode != MIR_OP_HARD_REG) {
// ??? to optimize (can be immediate operand for func call)
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) { /* calculate offset for blk params */
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (call_insn->ops[i].mode == MIR_OP_MEM) {
type = call_insn->ops[i].u.mem.type;
gen_assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
gen_assert (!MIR_all_blk_type_p (type) || call_insn->ops[i].mode == MIR_OP_MEM);
if ((MIR_T_I8 <= type && type <= MIR_T_U64) || type == MIR_T_P || type == MIR_T_LD
|| MIR_all_blk_type_p (type)) {
if (MIR_blk_type_p (type) && (qwords = (call_insn->ops[i].u.mem.disp + 7) / 8) <= 2) {
if (type == MIR_T_BLK + 1) int_arg_num = (int_arg_num + 1) / 2 * 2; /* Make even */
if (int_arg_num + qwords > 8)
blk_offset += (qwords - (int_arg_num + qwords == 9 ? 1 : 0)) * 8;
int_arg_num += qwords;
} else { /* blocks here are passed by address */
if (type == MIR_T_LD) int_arg_num = (int_arg_num + 1) / 2 * 2; /* Make even */
if (int_arg_num >= 8) blk_offset += 8 + (type == MIR_T_LD ? 8 : 0);
int_arg_num++;
if (type == MIR_T_LD) int_arg_num++;
}
} else if (type == MIR_T_F || type == MIR_T_D) {
if (i - start >= nargs) { /* varargs are passed by int regs */
if (int_arg_num >= 8) blk_offset += 8;
int_arg_num++;
} else {
if (fp_arg_num >= 8) blk_offset += 8;
fp_arg_num++;
}
} else {
MIR_get_error_func (ctx) (MIR_call_op_error, "wrong type of arg value");
}
}
blk_offset = (blk_offset + 15) / 16 * 16; /* align stack */
int_arg_num = fp_arg_num = 0;
for (size_t i = start; i < nops; i++) {
arg_op = call_insn->ops[i];
gen_assert (arg_op.mode == MIR_OP_REG || arg_op.mode == MIR_OP_HARD_REG
|| (arg_op.mode == MIR_OP_MEM && MIR_all_blk_type_p (arg_op.u.mem.type)));
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (call_insn->ops[i].mode == MIR_OP_MEM) {
type = call_insn->ops[i].u.mem.type;
gen_assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
ext_insn = NULL;
if ((ext_code = get_ext_code (type, TRUE)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
gen_assert (
!MIR_all_blk_type_p (type)
|| (arg_op.mode == MIR_OP_MEM && arg_op.u.mem.disp >= 0 && arg_op.u.mem.index == 0));
if (MIR_blk_type_p (type)) {
qwords = (arg_op.u.mem.disp + 7) / 8;
if (qwords <= 2) {
arg_reg = A0_HARD_REG + int_arg_num;
if (type == MIR_T_BLK + 1) int_arg_num = (int_arg_num + 1) / 2 * 2; /* Make even */
for (int n = 0; n < qwords; n++) {
if (int_arg_num < 8) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, A0_HARD_REG + int_arg_num),
MIR_new_mem_op (ctx, MIR_T_I64, n * 8, arg_op.u.mem.base, 0, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
setup_call_hard_reg_args (gen_ctx, call_insn, A0_HARD_REG + int_arg_num);
int_arg_num++;
} else { /* put word on stack */
treg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn
= MIR_new_insn (ctx, MIR_MOV, treg_op,
MIR_new_mem_op (ctx, MIR_T_I64, n * 8, arg_op.u.mem.base, 0, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
mem_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, mem_size, SP_HARD_REG,
MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_MOV, mem_op, treg_op);
gen_add_insn_before (gen_ctx, call_insn, new_insn);
mem_size += 8;
}
}
continue;
}
/* Put on stack and pass the address: */
gen_blk_mov (gen_ctx, call_insn, blk_offset, SP_HARD_REG, arg_op.u.mem.base, qwords,
int_arg_num);
arg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
gen_assert (curr_prev_call_insn
!= NULL); /* call_insn should not be 1st after simplification */
new_insn
= MIR_new_insn (gen_ctx->ctx, MIR_ADD, arg_op, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
MIR_new_int_op (ctx, blk_offset));
gen_add_insn_after (gen_ctx, curr_prev_call_insn, new_insn);
curr_prev_call_insn = DLIST_NEXT (MIR_insn_t, new_insn);
blk_offset += qwords * 8;
}
if ((arg_reg
= get_arg_reg (type, i - start >= nargs, &int_arg_num, &fp_arg_num, &new_insn_code))
!= MIR_NON_HARD_REG) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
if (type != MIR_T_RBLK) {
if (new_insn_code == MIR_MOV && (type == MIR_T_F || type == MIR_T_D)) {
new_insn
= _MIR_new_unspec_insn (ctx, 3,
MIR_new_int_op (ctx, type == MIR_T_F ? FMVXW_CODE : FMVXD_CODE),
arg_reg_op, arg_op);
} else {
new_insn = MIR_new_insn (ctx, new_insn_code, arg_reg_op, arg_op);
}
} else {
assert (arg_op.mode == MIR_OP_MEM);
new_insn = MIR_new_insn (ctx, MIR_MOV, arg_reg_op, MIR_new_reg_op (ctx, arg_op.u.mem.base));
arg_reg_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_RBLK, arg_op.u.mem.disp, arg_reg,
MIR_NON_HARD_REG, 1);
}
gen_add_insn_before (gen_ctx, call_insn, new_insn);
call_insn->ops[i] = arg_reg_op;
if (type == MIR_T_LD) /* long double is passed in 2 int hard regs: */
setup_call_hard_reg_args (gen_ctx, call_insn, arg_reg + 1);
} else { /* put arguments on the stack */
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code = (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: type == MIR_T_LD ? MIR_LDMOV
: MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
if (type != MIR_T_RBLK) {
new_insn = MIR_new_insn (ctx, new_insn_code, mem_op, arg_op);
} else {
assert (arg_op.mode == MIR_OP_MEM);
new_insn
= MIR_new_insn (ctx, new_insn_code, mem_op, MIR_new_reg_op (ctx, arg_op.u.mem.base));
}
gen_assert (curr_prev_call_insn != NULL); /* call should not be 1st after simplification */
MIR_insert_insn_after (ctx, curr_func_item, curr_prev_call_insn, new_insn);
prev_insn = DLIST_PREV (MIR_insn_t, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, prev_insn, next_insn, call_insn);
call_insn->ops[i] = mem_op;
mem_size += type == MIR_T_LD ? 16 : 8;
if (ext_insn != NULL) gen_add_insn_after (gen_ctx, curr_prev_call_insn, ext_insn);
}
}
blk_offset = (blk_offset + 15) / 16 * 16;
if (blk_offset != 0) mem_size = blk_offset;
int_arg_num = fp_arg_num = 0;
for (size_t i = 0; i < proto->nres; i++) {
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_REG || ret_reg_op.mode == MIR_OP_HARD_REG);
type = proto->res_types[i];
float_p = type == MIR_T_F || type == MIR_T_D;
if (float_p && fp_arg_num < 2) {
new_insn = MIR_new_insn (ctx, type == MIR_T_F ? MIR_FMOV : MIR_DMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, FA0_HARD_REG + fp_arg_num));
fp_arg_num++;
} else if (type == MIR_T_LD && int_arg_num < 2) {
new_insn = MIR_new_insn (ctx, MIR_LDMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, A0_HARD_REG + int_arg_num));
int_arg_num += 2;
} else if (!float_p && int_arg_num < 2) {
new_insn = MIR_new_insn (ctx, MIR_MOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, A0_HARD_REG + int_arg_num));
int_arg_num++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"riscv can not handle this combination of return values");
}
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (type, FALSE)) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (gen_ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
if (mem_size != 0) { /* allocate/deallocate stack for args passed on stack */
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
mem_size = (mem_size + 15) / 16 * 16; /* make it of several 16 bytes */
new_insn = MIR_new_insn (ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), temp_op);
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, MIR_new_int_op (ctx, -(int64_t) mem_size));
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
create_new_bb_insns (gen_ctx, prev_call_insn, next_insn, call_insn);
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
new_insn = MIR_new_insn (ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), temp_op);
MIR_insert_insn_before (ctx, curr_func_item, next_insn, new_insn);
create_new_bb_insns (gen_ctx, call_insn, next_insn, call_insn);
}
}
static long double mir_i2ld (int64_t i) { return i; }
static const char *I2LD = "mir.i2ld";
static const char *I2LD_P = "mir.i2ld.p";
static long double mir_ui2ld (uint64_t i) { return i; }
static const char *UI2LD = "mir.ui2ld";
static const char *UI2LD_P = "mir.ui2ld.p";
static long double mir_f2ld (float f) { return f; }
static const char *F2LD = "mir.f2ld";
static const char *F2LD_P = "mir.f2ld.p";
static long double mir_d2ld (double d) { return d; }
static const char *D2LD = "mir.d2ld";
static const char *D2LD_P = "mir.d2ld.p";
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *LD2I = "mir.ld2i";
static const char *LD2I_P = "mir.ld2i.p";
static float mir_ld2f (long double ld) { return ld; }
static const char *LD2F = "mir.ld2f";
static const char *LD2F_P = "mir.ld2f.p";
static double mir_ld2d (long double ld) { return ld; }
static const char *LD2D = "mir.ld2d";
static const char *LD2D_P = "mir.ld2d.p";
static long double mir_ldadd (long double d1, long double d2) { return d1 + d2; }
static const char *LDADD = "mir.ldadd";
static const char *LDADD_P = "mir.ldadd.p";
static long double mir_ldsub (long double d1, long double d2) { return d1 - d2; }
static const char *LDSUB = "mir.ldsub";
static const char *LDSUB_P = "mir.ldsub.p";
static long double mir_ldmul (long double d1, long double d2) { return d1 * d2; }
static const char *LDMUL = "mir.ldmul";
static const char *LDMUL_P = "mir.ldmul.p";
static long double mir_lddiv (long double d1, long double d2) { return d1 / d2; }
static const char *LDDIV = "mir.lddiv";
static const char *LDDIV_P = "mir.lddiv.p";
static long double mir_ldneg (long double d) { return -d; }
static const char *LDNEG = "mir.ldneg";
static const char *LDNEG_P = "mir.ldneg.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static const char *VA_BLOCK_ARG_P = "mir.va_block_arg.p";
static const char *VA_BLOCK_ARG = "mir.va_block_arg";
static int64_t mir_ldeq (long double d1, long double d2) { return d1 == d2; }
static const char *LDEQ = "mir.ldeq";
static const char *LDEQ_P = "mir.ldeq.p";
static int64_t mir_ldne (long double d1, long double d2) { return d1 != d2; }
static const char *LDNE = "mir.ldne";
static const char *LDNE_P = "mir.ldne.p";
static int64_t mir_ldlt (long double d1, long double d2) { return d1 < d2; }
static const char *LDLT = "mir.ldlt";
static const char *LDLT_P = "mir.ldlt.p";
static int64_t mir_ldge (long double d1, long double d2) { return d1 >= d2; }
static const char *LDGE = "mir.ldge";
static const char *LDGE_P = "mir.ldge.p";
static int64_t mir_ldgt (long double d1, long double d2) { return d1 > d2; }
static const char *LDGT = "mir.ldgt";
static const char *LDGT_P = "mir.ldgt.p";
static int64_t mir_ldle (long double d1, long double d2) { return d1 <= d2; }
static const char *LDLE = "mir.ldle";
static const char *LDLE_P = "mir.ldle.p";
static int get_builtin (gen_ctx_t gen_ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_I2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, I2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, I2LD, mir_i2ld);
return 1;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
return 1;
case MIR_F2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, F2LD_P, 1, &res_type, 1, MIR_T_F, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, F2LD, mir_f2ld);
return 1;
case MIR_D2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, D2LD_P, 1, &res_type, 1, MIR_T_D, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, D2LD, mir_d2ld);
return 1;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
return 1;
case MIR_LD2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2F_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2F, mir_ld2f);
return 1;
case MIR_LD2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2D_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2D, mir_ld2d);
return 1;
case MIR_LDADD:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDADD_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDADD, mir_ldadd);
return 2;
case MIR_LDSUB:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDSUB_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDSUB, mir_ldsub);
return 2;
case MIR_LDMUL:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDMUL_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDMUL, mir_ldmul);
return 2;
case MIR_LDDIV:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDDIV_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDDIV, mir_lddiv);
return 2;
case MIR_LDNEG:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LDNEG_P, 1, &res_type, 1, MIR_T_LD, "d");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNEG, mir_ldneg);
return 1;
case MIR_LDEQ:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDEQ_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDEQ, mir_ldeq);
return 2;
case MIR_LDNE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDNE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNE, mir_ldne);
return 2;
case MIR_LDLT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLT, mir_ldlt);
return 2;
case MIR_LDGE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGE, mir_ldge);
return 2;
case MIR_LDGT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGT, mir_ldgt);
return 2;
case MIR_LDLE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLE, mir_ldle);
return 2;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
return 2;
case MIR_VA_BLOCK_ARG:
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, VA_BLOCK_ARG_P, 0, NULL, 4, MIR_T_I64,
"res", MIR_T_I64, "va", MIR_T_I64, "size", MIR_T_I64, "ncase");
*func_import_item
= _MIR_builtin_func (ctx, curr_func_item->module, VA_BLOCK_ARG, va_block_arg_builtin);
return 4;
default: return 0;
}
}
DEF_VARR (int);
DEF_VARR (uint8_t);
DEF_VARR (uint64_t);
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
struct label_ref {
int abs_addr_p, short_p;
size_t label_val_disp;
MIR_label_t label;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
struct const_ref {
uint64_t val;
size_t const_addr_disp;
};
typedef struct const_ref const_ref_t;
DEF_VARR (const_ref_t);
DEF_VARR (MIR_code_reloc_t);
struct target_ctx {
unsigned char alloca_p, block_arg_func_p, leaf_p;
uint32_t non_vararg_int_args_num;
size_t small_aggregate_save_area;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (label_ref_t) * label_refs;
VARR (const_ref_t) * const_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define block_arg_func_p gen_ctx->target_ctx->block_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define non_vararg_int_args_num gen_ctx->target_ctx->non_vararg_int_args_num
#define small_aggregate_save_area gen_ctx->target_ctx->small_aggregate_save_area
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define label_refs gen_ctx->target_ctx->label_refs
#define const_refs gen_ctx->target_ctx->const_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static MIR_disp_t target_get_stack_slot_offset (gen_ctx_t gen_ctx, MIR_type_t type,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
size_t offset = curr_func_item->u.func->vararg_p || block_arg_func_p ? 32 : 16;
return ((MIR_disp_t) slot * 8 + offset);
}
static int target_valid_mem_offset_p (gen_ctx_t gen_ctx, MIR_type_t type, MIR_disp_t offset) {
MIR_disp_t offset2 = type == MIR_T_LD ? offset + 8 : offset;
return -(1 << 11) <= offset && offset2 < (1 << 11);
}
static void target_machinize (gen_ctx_t gen_ctx) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_type_t type, mem_type, res_type;
MIR_insn_code_t code, ext_code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn, anchor;
MIR_var_t var;
MIR_reg_t ret_reg, arg_reg;
MIR_op_t ret_reg_op, arg_reg_op, mem_op, temp_op, treg_op;
size_t i, int_arg_num, fp_arg_num, mem_size, qwords;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
block_arg_func_p = FALSE;
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
small_aggregate_save_area = 0;
for (i = int_arg_num = fp_arg_num = mem_size = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem|stack addr ... */
var = VARR_GET (MIR_var_t, func->vars, i);
type = var.type;
if (MIR_blk_type_p (type) && (qwords = (var.size + 7) / 8) <= 2) {
if (type == MIR_T_BLK + 1) int_arg_num = (int_arg_num + 1) / 2 * 2; /* Make even */
if (int_arg_num < 8) {
MIR_insn_code_t mov_code1 = MIR_MOV;
MIR_type_t mem_type1 = MIR_T_I64;
MIR_reg_t base_arg_reg = A0_HARD_REG;
size_t arg_reg_num = int_arg_num;
small_aggregate_save_area += qwords * 8;
gen_assert (small_aggregate_save_area < (1 << 11));
new_insn = MIR_new_insn (ctx, MIR_ADD, MIR_new_reg_op (ctx, i + 1),
_MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, -(int64_t) small_aggregate_save_area));
gen_add_insn_before (gen_ctx, anchor, new_insn);
if (qwords == 0) continue;
gen_mov (gen_ctx, anchor, mov_code1, MIR_new_mem_op (ctx, mem_type1, 0, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, base_arg_reg + arg_reg_num));
if (qwords == 2) {
MIR_insn_code_t mov_code2 = MIR_MOV;
MIR_type_t mem_type2 = MIR_T_I64;
MIR_disp_t disp = 8;
if (arg_reg_num < 7) {
gen_mov (gen_ctx, anchor, mov_code2, MIR_new_mem_op (ctx, mem_type2, disp, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, base_arg_reg + arg_reg_num + 1));
} else {
if (!block_arg_func_p) { /* t0 = prev sp */
block_arg_func_p = TRUE;
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, T0_HARD_REG),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_HARD_REG,
1));
}
treg_op = _MIR_new_hard_reg_op (ctx, T1_HARD_REG);
gen_mov (gen_ctx, anchor, mov_code2, treg_op,
_MIR_new_hard_reg_mem_op (ctx, mem_type2, mem_size, T0_HARD_REG,
MIR_NON_HARD_REG, 1));
gen_mov (gen_ctx, anchor, mov_code2, MIR_new_mem_op (ctx, mem_type2, disp, i + 1, 0, 1),
treg_op);
mem_size += 8;
}
}
int_arg_num += qwords;
} else { /* fully on stack -- use the address: */
if (!block_arg_func_p) { /* t0 = prev sp */
block_arg_func_p = TRUE;
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, T0_HARD_REG),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_HARD_REG, 1));
}
new_insn
= MIR_new_insn (ctx, MIR_ADD, MIR_new_reg_op (ctx, i + 1),
_MIR_new_hard_reg_op (ctx, T0_HARD_REG), MIR_new_int_op (ctx, mem_size));
gen_add_insn_before (gen_ctx, anchor, new_insn);
mem_size += qwords * 8;
}
continue;
}
arg_reg = get_arg_reg (type, FALSE, &int_arg_num, &fp_arg_num, &new_insn_code);
if (arg_reg != MIR_NON_HARD_REG) {
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
gen_mov (gen_ctx, anchor, new_insn_code, MIR_new_reg_op (ctx, i + 1), arg_reg_op);
} else { /* arg is on the stack or blk address is on the stack: */
if (!block_arg_func_p) {
block_arg_func_p = TRUE;
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_hard_reg_op (ctx, T0_HARD_REG),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_HARD_REG, 1));
}
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code = (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: type == MIR_T_LD ? MIR_LDMOV
: MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, T0_HARD_REG, MIR_NON_HARD_REG, 1);
gen_mov (gen_ctx, anchor, new_insn_code, MIR_new_reg_op (ctx, i + 1), mem_op);
mem_size += type == MIR_T_LD ? 16 : 8;
}
}
non_vararg_int_args_num = int_arg_num;
alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
MIR_item_t proto_item, func_import_item;
int nargs;
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
switch (code) {
case MIR_FBEQ: code = MIR_FEQ; break;
case MIR_FBNE: code = MIR_FNE; break;
case MIR_FBLT: code = MIR_FLT; break;
case MIR_FBGE: code = MIR_FGE; break;
case MIR_FBGT: code = MIR_FGT; break;
case MIR_FBLE: code = MIR_FLE; break;
case MIR_DBEQ: code = MIR_DEQ; break;
case MIR_DBNE: code = MIR_DNE; break;
case MIR_DBLT: code = MIR_DLT; break;
case MIR_DBGE: code = MIR_DGE; break;
case MIR_DBGT: code = MIR_DGT; break;
case MIR_DBLE: code = MIR_DLE; break;
case MIR_LDBEQ: code = MIR_LDEQ; break;
case MIR_LDBNE: code = MIR_LDNE; break;
case MIR_LDBLT: code = MIR_LDLT; break;
case MIR_LDBGE: code = MIR_LDGE; break;
case MIR_LDBGT: code = MIR_LDGT; break;
case MIR_LDBLE: code = MIR_LDLE; break;
case MIR_EQS:
case MIR_NES:
case MIR_BEQS:
case MIR_BNES:
case MIR_LTS:
case MIR_LES:
case MIR_GTS:
case MIR_GES:
case MIR_BLTS:
case MIR_BLES:
case MIR_BGTS:
case MIR_BGES: ext_code = MIR_EXT32; goto short_cmp;
case MIR_ULTS:
case MIR_ULES:
case MIR_UGTS:
case MIR_UGES:
case MIR_UBLTS:
case MIR_UBLES:
case MIR_UBGTS:
case MIR_UBGES:
ext_code = MIR_UEXT32;
short_cmp:
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, ext_code, temp_op, insn->ops[1]);
gen_add_insn_before (gen_ctx, insn, new_insn);
treg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, ext_code, treg_op, insn->ops[2]);
gen_add_insn_before (gen_ctx, insn, new_insn);
insn->ops[1] = temp_op;
insn->ops[2] = treg_op;
break;
default: break;
}
if (code != insn->code) {
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, code, temp_op, insn->ops[1], insn->ops[2]);
gen_add_insn_before (gen_ctx, insn, new_insn);
next_insn = MIR_new_insn (ctx, MIR_BT, insn->ops[0], temp_op);
gen_add_insn_after (gen_ctx, new_insn, next_insn);
gen_delete_insn (gen_ctx, insn);
insn = new_insn;
}
if ((nargs = get_builtin (gen_ctx, code, &proto_item, &func_import_item)) > 0) {
if (code == MIR_VA_ARG || code == MIR_VA_BLOCK_ARG) {
/* Use a builtin func call:
mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
reg3 */
MIR_op_t ops[6], func_reg_op, reg_op3;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], op3 = insn->ops[2];
assert (res_reg_op.mode == MIR_OP_REG && va_reg_op.mode == MIR_OP_REG