[Feature] clock/reset type cast

[taichi-ishitani]

refs: #622 (comment)

To connect clock/reset signals having different types, we need to introduce clock/reset type cast.
When an operand and a cast type have different polarity, an inverter logic will be inserted.

Veryl code

var rst_a: reset;
var rst_b: reset_async_high;
var rst_c: reset_async_low;

always_comb {
  rst_b = rst_a as reset_async_high;
  rst_c = rst_a as reset_async_low;
}

Generated SV code

logic rst_a;
logic rst_b;
logic rst_c;

always_comb begin
  rst_b = rst_a;
  rst_c = ~rst_a;
end