var declaration with same name as enum member

[nananapo]

module ModuleA () {
    enum EnumName: logic {
        MemberName,
    }
    var EnumName_MemberName: logic;
    always_comb {
        EnumName_MemberName = 0;
    }
}

This Veryl code is translated into

module project_ModuleA ();
    typedef enum logic {
        EnumName_MemberName
    } EnumName;
    logic EnumName_MemberName;
    always_comb begin
        EnumName_MemberName = 0;
    end
endmodule

The member of EnumName is instantiated as EnumName_MemberName.
This may be ambiguous when there are var declarations with same name.

I don't know this is legal in SystemVerilog, but verilator, iverilog and GOWIN EDA don't support it. So I think prohibiting same name declaration as enum member or emitting another name is good.