SDC support

[dalance]

If Veryl can identify clock and reset by #622, SDC support like auto generation and consistency check can be added.

[nblei]

I think there's a very powerful idea here, Naoya.

Rather than writing synthesis scripts in some typeless scripting language which has no understanding of the Verilog modules being synthesized, doesn't it make sense to write synthesis scripts in a language with tooling which can parse and extract meaning from the HDL?

In other words, can we leverage the LSP and semantic checks of Veryl to provide a powerful DSL which transpiles into tcl synthesis scripts?

[dalance]

I thought handling SDC directly, but a specialized language which can be transpiled into TCL may be better surely.