{"payload":{"header_redesign_enabled":false,"results":[{"id":"36567136","archived":false,"color":"#b2b7f8","followers":643,"has_funding_file":true,"hl_name":"ultraembedded/cores","hl_trunc_description":"Various HDL (Verilog) IP Cores","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":36567136,"name":"cores","owner_id":7809581,"owner_login":"ultraembedded","updated_at":"2021-07-01T16:43:34.664Z","has_issues":true}},"sponsorable":true,"topics":["audio","asic","fpga","usb","rtl","verilog","spi","sram","uart","verilog-hdl","verilog-components","verilator","i2s","sdram"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":50,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aultraembedded%252Fcores%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ultraembedded/cores/star":{"post":"E9GDWd1_HbbF6OcTdCLLjdRROMsEeWObn0MA8SNYawgKCddfVYcg6Ef7QbcxEwLAzm03z_R08D9az3gQrwxcfg"},"/ultraembedded/cores/unstar":{"post":"piD2efuVMm-Eqozz1YuEnBTuoXtqwlHlALkR7G_9zhtvQvloIYa2GPUrDEGt7Xlipd8gaybZnh1tsdZTSBaTuA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"t1wsQOFa7s-QGhQGOVceePbSExxD_T-3rJc06p8_Mbo-I8dRpD4j9uywxRcrsjYzDN-ibLw1qlBrXUhFeeG8Qg"}}},"title":"Repository search results"}