Please add MSVC builds to travis CI

[apriori]

Currently triSYCL does not build with MSVC 2017, mostly due to unsupported attribute statements used.

An exerpt:

 git grep -i noinline
include/triSYCL/detail/instantiate_kernel.hpp:    this function marked as \c noinline, otherwise the kernel code is
include/triSYCL/detail/instantiate_kernel.hpp:    seems incompatible with \c noinline in Clang/LLVM 3.9.1, because
include/triSYCL/detail/instantiate_kernel.hpp:__declspec(noinline) void
include/triSYCL/detail/instantiate_kernel.hpp:    The \c noinline attribute is used to force this to appear as a
include/triSYCL/detail/instantiate_kernel.hpp:__declspec(noinline)
include/triSYCL/vendor/Xilinx/fpga/ssdm_inst.hpp:    __attribute__ ((nothrow, noinline, weak));
include/triSYCL/vendor/Xilinx/fpga/ssdm_inst.hpp:  void _ssdm_op_SpecPipeline(...) __attribute__ ((nothrow, noinline, weak));
include/triSYCL/vendor/Xilinx/fpga/ssdm_inst.hpp:  void _ssdm_SpecArrayPartition(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/array_partition_cyclicblock.cpp:  void _ssdm_op_SpecPipeline(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/array_partition_cyclicblock.cpp:  void _ssdm_SpecArrayPartition(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/single_task_vector_add_automatic_array_dataflow_drt.cpp:  void _ssdm_op_SpecDataflowPipeline(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/single_task_vector_add_automatic_array_dataflow_drt.cpp:  void _ssdm_op_SpecPipeline(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/single_task_vector_add_drt_dataflow_func.cpp:  void _ssdm_op_SpecDataflowPipeline(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/single_task_vector_add_drt_dataflow_func_local_pipeline.cpp:  void _ssdm_op_SpecDataflowPipeline(...) __attribute__ ((nothrow, noinline, weak));
tests/device_compiler/single_task_vector_add_drt_dataflow_func_local_pipeline.cpp:  void _ssdm_op_SpecPipeline(...) __attribute__ ((nothrow, noinline, weak));

trisycl\include\trisycl\device_runtime.hpp(120): error C2496: 'serialize_arg': 'selectany' can only be applied to data items with external linkage
trisycl\include\trisycl\device_runtime.hpp(141): error C2496: 'serialize_accessor_arg': 'selectany' can only be applied to data items with external linkage
trisycl\include\trisycl\device_runtime.hpp(201): error C2496: 'set_kernel': 'selectany' can only be applied to data items with external linkage

[keryell]

I do not have MSVC experience.
Perhaps you should start by using the latest version of MSVC?
Anyway all these errors are in the Xilinx-specific device code that requires the Clang/LLVM device compiler.
So right now, even it compile on the host side, there is no chance to run with Clang/LLVM on FPGA for now. So using triSYCL here with MSVC will not help.

[MathiasMagnus]

If you don't mind having a different runner type of runner, having Azure Pipelines for MSVC isn't much effort. It has infinite CPU hours for OSS CI purposes. I've already setup a self-hosted version of it, but Azure host is simpler to maintain.

The real question is whether the project wants MSVC support, even if at times it may block PRs and need a little extra effort.

[keryell]

Even if the current design cannot support Xilinx devices, it might be interesting to still run with CPU.
But some other SYCL implementations can do this too...
@MathiasMagnus you are the one who added MSVC support at the first place, so I leave this decision to you. :-)

[feliwir]

You could run all 3 platforms on Github Actions

[keryell]

You could run all 3 platforms on Github Actions

Feel free to contribute, if you know how to do it. :-)

[keryell]

Now we have moved to Github Actions, it is possible to make progress on this.