Computer Architecture course project - ECE, Technical University of Crete
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Updated
May 7, 2022 - VHDL
Computer Architecture course project - ECE, Technical University of Crete
Simulation of Tomasulo algorithm in python
Simulates Tomasulo Algorithms with Reorder Buffer
A simulator for the Tomasulo algorithm. It accepts MIPS instructions and shows step by step how these instructions are executed as well as the content of each component in the Tomasulo architecture
This was a semester project for Computer Architecture course
A customizable Tomasolu simulator built with Flutter
The architectural simulator follows Tomasulo’s algorithm without speculation (no reorder buffer involved). The instructions supported are LOAD, STORE, BNE, JAL, RET, ADD, ADDI, NEG, NAND, and SLL. The number of reservation stations and execution cycles per functional unit is taken as input from the user. Implemented by: Nada Badawi & Maya Makram.
A RISC-V RV32I cpu simulator, featuring tomasulo algorithm and hardware speculation.
A simulator of the Tomasulo algorithm in javascript
CPU Resources Simulator using Tomasulo algorithm
Simulador do algoritmo de Tomasulo.
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
This is a VHDL implementation of the Tomasulo algorithm with Reorder Buffer within the university Lesson of Computer Architecture
A MIPS Processor Based on Tomasulo Algorithm
Simulador do Algoritmo de Tomasulo
A speculative tomasulo simulator with ROB(Reorder Buffer)
this project is for microprocessors enjoyers.
Computer Architecture Assignments (HY425) [winter semester of 2023].
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