Network on Chip Simulator
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Updated
Jan 22, 2024 - C++
Network on Chip Simulator
Network on Chip Implementation written in SytemVerilog
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
Official read only mirror for
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
A Chisel RTL generator for network-on-chip interconnects
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
cycle accurate Network-on-Chip Simulator
A Framework for System Modeling, Simulation, and Emulation
Optimal circulant graphs generating results dataset
ndn-hydra: A Python-coded NDN distributed repository with five focused attributes: resiliency, scalability, usability, efficiency, and security.
HLS for Networks-on-Chip
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
Ansible Playbook um das Toolbox Netzwerk zu deployen
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