Teaching Materials for Dr. Waleed A. Yousef
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Updated
Dec 18, 2022 - Mathematica
Teaching Materials for Dr. Waleed A. Yousef
EventNext is logic interface design actors components for .net core
Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic
All the homeworks, studies and projects I've done at Metu-CENG
SystemVerilog examples for a digital design course
Logic Minimization in Python
Projects of a CSE student at Marmara University
All the homeworks, testers and projects done at METU-CENG
Automated conversion from CHP to PRS using syntax-directed translation
A collection of digital logic circuits
Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog
An execution unit that is able to do the following commands: Move Value to Register, Move Register to Register, Add Value to Register, Add Register to Register, AND Value to Register and AND Register to Register.
Design and implementation the components of the SPI modules: Master, Slave and Self-Checking Testbenches for the Master and Slave. using verilog
A SimCirJS fork with enhanced functionalities
Homeworks given at Department of Computer Engineering, Middle East Technical University.
modelled encryption-decryption module using verilog. Given a text file, it can be encrypted using encryptor and can be decrypted later using decryptor.
This software is designed to help Computer/Electric Hardware Engineers design an efficient digital logic circuit with best optimisation for lowest cost and power consumption to implement any function.
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