Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
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Updated
Feb 21, 2024 - Verilog
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
Play and learn with the Terasic DE0-Atlas/Nano-SoC Kit featuring a Altera/Intel Cyclone V 5CSEMA4U23C6N FPGA with integrated dual-core ARM Cortex-A9.
Torii HDL Board Definitions
Serving object detection models on different hardware.
OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board
A Comprehensive Dataflow Compiler for High-Level Synthesis
High-Level Synthesis with Partial Evaluation
Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
Fletcher Open Programmable Acceleration Engine platform support
IntelFPGA configuration & Avalon-MM access library for FlashAir
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
SoC and Embedded Linux
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
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