A really fast, secure random file generator. Much faster than /dev/urandom.
-
Updated
Mar 11, 2017 - C++
A really fast, secure random file generator. Much faster than /dev/urandom.
doppioDB - A hardware accelerated database
CNN accelerator
Hardware Software Co-Design Course Project
Linear algebra accelerators for RISC-V (published in ICCD 17)
32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Android App which uses Hardware step sensor to keep track of daily and weekly step counts without any impact on battery.
Motion recognition with artificial intelligence on STM32
UltraZed Development
Subdivision surface approximation in real-time using hardware tesselation
Gravitational simulation of the N-body problem using FPGA hardware acceleration
Detailed level design of a chip that helps the CPU in computing the convolution process
A hardware accelerated AES implementation for the Embedded Parallel Operating System from LISHA/UFSC.
Binary Neural Network on IceStick FPGA.
A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.
A configurable processing element for deep neural network accelerators
browser based audio processing using the GPU
Convolutional Neural Networks for Verilog High-Level Synthesis
HLS SHA-3 Accelerator
Add a description, image, and links to the hardware-acceleration topic page so that developers can more easily learn about it.
To associate your repository with the hardware-acceleration topic, visit your repo's landing page and select "manage topics."