Behavioral architecture of a read/write cycle controller for a DRAM chip.
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Updated
May 26, 2023 - VHDL
Behavioral architecture of a read/write cycle controller for a DRAM chip.
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
MIPS ISA simulator which implements non-blocking DRAM access
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput
Commodore C386SX-LT 2MB memory module schematics
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
DRAM Request Manager for Multicore Processors
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/210…
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