CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
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Updated
May 27, 2024 - C
CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.
DDR2 memory controller written in Verilog
【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
mirror of https://git.elphel.com/Elphel/eddr3
DDAL(Distributed Data Access Layer) is a simple solution to access database shard.
New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
573controller allows you to transform an Arduino Leonardo or Micro into various 573 music game controllers
🎮 PIU simulator for the GBA.
Working fork of TapMania for iOS 9.3 and above.
Device Description Repository (DDR)
A linux-based tool to fix the Axis problem caused by PlayStation->USB adapters on DDR dance pads.
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
The Bug Reporting Repository for OutFox LTS 0.4, Alpha V and Steam Early Access Builds
A modern website for DDR stepcharts. Think of them like guitar tabs, but for the songs's dance steps in the game.
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