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Synthesizing the USB core with Intel Quartus Prime for a MAX 10 results in enumeration failure with the latest master. I'm using the same 48Mhz clock for clk and clk_48mhz as there is currently a single clock domain in my design but when plugging the device there's no response to the setup address phase. I bisected this to a0676aa (TinyFPGA_BX: use clock crossing strobe to bridge the 48 MHz USB clock). I haven't yet tried a higher or lower frequency clock for clk and don't have any Lattice devices to try the same setup with.
The text was updated successfully, but these errors were encountered:
Synthesizing the USB core with Intel Quartus Prime for a MAX 10 results in enumeration failure with the latest master. I'm using the same 48Mhz clock for clk and clk_48mhz as there is currently a single clock domain in my design but when plugging the device there's no response to the setup address phase. I bisected this to a0676aa (TinyFPGA_BX: use clock crossing strobe to bridge the 48 MHz USB clock). I haven't yet tried a higher or lower frequency clock for clk and don't have any Lattice devices to try the same setup with.
The text was updated successfully, but these errors were encountered: