nexys_video video target fails with missing pix5x_o clock domain

[mithro]

The PLATFORM=nexys_video TARGET=video currently fails complaining about a missing pix5x_o clock domain.

I assume something is not renaming pix5x_o to hdmi_out0_pix5x. Most certainly caused by upstream changes in litevideo.

See https://travis-ci.org/mithro/HDMI2USB-litex-firmware/jobs/423460199

make[1]: Leaving directory `/home/travis/build/mithro/HDMI2USB-litex-firmware/build/nexys_video_video_lm32/software/firmware'
available clock domains:
sys
sys4x
sys4x_dqs
clk200
clk100
eth_rx
eth_tx
eth_tx90
hdmi_in0_pix
pix1p25x
hdmi_in0_pix5x
data0_cap_write
data0_cap_read
data1_cap_write
data1_cap_read
data2_cap_write
data2_cap_read
fmeter
hdmi_out0_pix
hdmi_out0_pix5x
Traceback (most recent call last):
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/gen/fhdl/verilog.py", line 360, in convert
    f.clock_domains[cd_name]
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/migen/migen/fhdl/structure.py", line 739, in __getitem__
    raise KeyError(key)
KeyError: 'pix5x_o'
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
  File "./make.py", line 143, in <module>
    main()
  File "./make.py", line 127, in main
    vns = builder.build(**dict(args.build_option))
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/builder.py", line 167, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 356, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/platform.py", line 43, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/vivado.py", line 222, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/platform.py", line 37, in get_verilog
    special_overrides=so, attr_translate=self.toolchain.attr_translate, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/home/travis/build/mithro/HDMI2USB-litex-firmware/third_party/litex/litex/gen/fhdl/verilog.py", line 370, in convert
    raise KeyError("Unresolved clock domain: '"+cd_name+"'")
KeyError: "Unresolved clock domain: 'pix5x_o'"
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