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Minimal spi master #207

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@dehanj dehanj commented Apr 18, 2024 •
edited by mchack-work

This supersedes #203

This PR adds a minimal SPI master to the application_fpga. This allows applications to access the Flash memory on the Tkey. The SPI master basically supports generating a clock, control the chip select, and send and receive a byte. SW much implement the functionality required to send commands and receive responses. Updates to tkey_libs will add this functionality.

Currently the SPI master is enabled in FPGA builds by including the flag symbol INCLUDE_SPI_MASTER to Yosys in the Makefile. The Makefile does not yet change pin constraint file. Instead the constraint file now always includes pins for the SPI interface.

Rebased on main, and squashed.

  • SPI master construction (also added a job to CI)
  • Testbench and simulation

Closes #213

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dehanj commented Apr 18, 2024

To minimize the risk during rebase and squash I created a new branch and a new PR.
I suggest we merge this isntead of #203 when we are ready and have tested it properly.

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dehanj commented Apr 18, 2024

I have verified both the builds with and without the SPI master. So far it looks good.

@dehanj dehanj force-pushed the minimal_spi_master_rebase branch 3 times, most recently from 54c1329 to ae1433a Compare April 19, 2024 07:46
@dehanj dehanj mentioned this pull request Apr 19, 2024
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@dehanj dehanj changed the title Minimal spi master rebase Minimal spi master Apr 19, 2024
@dehanj dehanj marked this pull request as ready for review April 19, 2024 08:23
@dehanj dehanj force-pushed the minimal_spi_master_rebase branch 2 times, most recently from 5c829a2 to 8c325ef Compare April 19, 2024 10:36
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dehanj commented Apr 19, 2024

This PR should be merged after #208, since it is a risk here that cache fetches the wrong bitstream.

secworks
secworks requested changes Apr 22, 2024
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hw/application_fpga/core/tk1/tb/tb_tk1.v
@@ -58,6 +58,10 @@ module tb_tk1();
localparam ADDR_CPU_MON_FIRST = 8'h61;
localparam ADDR_CPU_MON_LAST = 8'h62;

localparam ADDR_SPI_EN = 8'h80;
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Här skulle vi nog också ifdef:a.

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I don't have the answer if we should use ifdef in the tb as well. One argument is that it is easier to have on build and make sure it all works. But on the other hand, if it is substantial difference and it is a risk that the test fails, yeah then it is better to have two.

But I think you will have to answer for what is the best approach here Joachim.

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Having excess symbolic names should pose not problem. A linter may give warnings (This is not Go after all).
But ports in the DUT and associated wires should cause at least warnings during build of the som environment, and cause confusion. Testbench functionality such a state monitor, state display may also become problematic.

And most importantly. The test cases in a testbench should test the functionality of the DUT. This means that the DUT and the TB are in sync in terms of functionality. A self-checking test case that tests a functionality that don't exist in the DUT should fail.

To summarize. If we have functionality in the DUT (the core) that is compile time optional, we should also have the test functionality for that functionality compile time optional.

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@dehanj dehanj Apr 29, 2024 •
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Sounds great. Can you add, test and verify it?

hw/application_fpga/core/tk1/tb/tb_tk1.v
@@ -89,13 +93,24 @@ module tb_tk1();
wire tb_gpio3;
wire tb_gpio4;

wire tb_spi_ss;
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Mer ifdef.

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See my response in the other comment.

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Ok.

hw/application_fpga/Makefile Outdated Show resolved Hide resolved
@dehanj dehanj force-pushed the minimal_spi_master_rebase branch 2 times, most recently from 00e177a to fdea1bd Compare April 25, 2024 08:48
@mchack-work mchack-work requested review from mchack-work and removed request for mchack-work May 7, 2024 07:27
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SPI control addresses were missing from tk1_mem.h. I added them.

@secworks @dehanj
A construction of a minimal SPI master.
01a754c 
- NOTE: This is an optional feature, not built by default. Not included
  in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
  YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
@secworks @dehanj
Adding testbench and simulation targets for the SPI master.
afa28ab
@dehanj dehanj force-pushed the minimal_spi_master_rebase branch from fbd68eb to afa28ab Compare May 13, 2024 10:36
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@secworks secworks secworks requested changes

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Hardware support to access flash from CPU
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@dehanj @mchack-work @secworks