USART: Support half-duplex mode

[wjbuys]

The STM32G0x0 USART peripherals support a 1-wire half-duplex mode. From the reference manual:

26.5.15 USART single-wire Half-duplex communication

Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared:

• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.
  The USART can be configured to follow a Single-wire Half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and Full-duplex communication is made with a control bit HDSEL in USART_CR3.
  As soon as HDSEL is written to ‘1’:
• The TX and RX lines are internally connected.
• The RX pin is no longer used.
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up.
  Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter). In particular, the transmission is never blocked by hardware and continues as soon as data are written in the data register while the TE bit is set.

The only other rust implementation I've been able to find is from the stm32l4xx-hal crate, but it looks like that is using a different style of configuration, so it wouldn't be a straight port.

I'd be happy to try and contribute this, but I'll need a couple of pointers (still pretty new to embedded rust).

[AJAY-NESTDIGITAL]

How can I update the control registers in programming part using STM32cubeIDE?