stm32g050.mmap

0x40000400 A PERIPHERAL TIM3
0x40000400 B  REGISTER CR1 (rw): control register 1
0x40000400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40000400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40000400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40000400 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40000400 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40000400 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
0x40000400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000404 B  REGISTER CR2 (rw): control register 2
0x40000404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000404 C   FIELD 04w03 MMS (rw): Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40000404 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40000408 B  REGISTER SMCR (rw): slave mode control register
0x40000408 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source
0x40000408 C   FIELD 04w03 TS1 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40000408 C   FIELD 07w01 MSM (rw): Master/Slave mode
0x40000408 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000408 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40000408 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40000408 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40000408 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4000040C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000040C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000040C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000040C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000040C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000040C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000040C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000040C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4000040C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000040C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000040C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000040C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000040C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000410 B  REGISTER SR (rw): status register
0x40000410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40000410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40000410 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40000410 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40000410 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40000410 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40000410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40000410 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40000410 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40000410 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40000414 B  REGISTER EGR (wo): event generation register
0x40000414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40000414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40000414 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40000414 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40000414 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40000414 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40000418 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40000418 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40000418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000418 C   FIELD 00w02 CC1S: Capture/Compare 1 selection
0x40000418 C   FIELD 02w01 OC1FE: Output compare 1 fast enable
0x40000418 C   FIELD 02w02 IC1PSC: Input capture 1 prescaler
0x40000418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40000418 C   FIELD 04w04 IC1F: Input capture 1 filter
0x40000418 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000418 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40000418 C   FIELD 08w02 CC2S: Capture/Compare 2 selection
0x40000418 C   FIELD 10w01 OC2FE: Output compare 2 fast enable
0x40000418 C   FIELD 10w02 IC2PSC: Input capture 2 prescaler
0x40000418 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000418 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40000418 C   FIELD 12w04 IC2F: Input capture 2 filter
0x40000418 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000418 C   FIELD 16w01 OC1M_3: Output compare 1 mode, bit 3
0x40000418 C   FIELD 24w01 OC2M_3: Output compare 2 mode, bit 3
0x4000041C B  REGISTER CCMR2_Input (rw): capture/compare mode register 2 (input mode)
0x4000041C B  REGISTER CCMR2_Output (rw): capture/compare mode register 2 (output mode)
0x4000041C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection
0x4000041C C   FIELD 00w02 CC3S: Capture/Compare 3 selection
0x4000041C C   FIELD 02w01 OC3FE: Output compare 3 fast enable
0x4000041C C   FIELD 02w02 IC3PSC: Input capture 3 prescaler
0x4000041C C   FIELD 03w01 OC3PE: Output compare 3 preload enable
0x4000041C C   FIELD 04w03 OC3M: Output compare 3 mode
0x4000041C C   FIELD 04w04 IC3F: Input capture 3 filter
0x4000041C C   FIELD 07w01 OC3CE: Output compare 3 clear enable
0x4000041C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection
0x4000041C C   FIELD 08w02 CC4S: Capture/Compare 4 selection
0x4000041C C   FIELD 10w01 OC4FE: Output compare 4 fast enable
0x4000041C C   FIELD 10w02 IC4PSC: Input capture 4 prescaler
0x4000041C C   FIELD 11w01 OC4PE: Output compare 4 preload enable
0x4000041C C   FIELD 12w03 OC4M: Output compare 4 mode
0x4000041C C   FIELD 12w04 IC4F: Input capture 4 filter
0x4000041C C   FIELD 15w01 OC4CE: Output compare 4 clear enable
0x4000041C C   FIELD 16w01 OC3M_3: Output compare 3 mode, bit 3
0x4000041C C   FIELD 24w01 OC4M_3: Output compare 4 mode, bit 3
0x40000420 B  REGISTER CCER (rw): capture/compare enable register
0x40000420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40000420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40000420 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40000420 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40000420 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40000420 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40000424 B  REGISTER CNT (rw): counter
0x40000424 C   FIELD 00w16 CNT_L: Low counter value
0x40000424 C   FIELD 16w16 CNT_H: High counter value (TIM2 only)
0x40000428 B  REGISTER PSC (rw): prescaler
0x40000428 C   FIELD 00w16 PSC: Prescaler value
0x4000042C B  REGISTER ARR (rw): auto-reload register
0x4000042C C   FIELD 00w32 ARR (rw): High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40000434 B  REGISTER CCR1 (rw): capture/compare register
0x40000434 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000438 B  REGISTER CCR2 (rw): capture/compare register
0x40000438 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x4000043C B  REGISTER CCR3 (rw): capture/compare register
0x4000043C C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000440 B  REGISTER CCR4 (rw): capture/compare register
0x40000440 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000448 B  REGISTER DCR (rw): DMA control register
0x40000448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40000448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4000044C B  REGISTER DMAR (rw): DMA address for full transfer
0x4000044C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40000460 B  REGISTER AF1 (rw): TIM alternate function option register 1
0x40000460 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved
0x40000468 B  REGISTER TISEL (rw): TIM alternate function option register 1
0x40000468 C   FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0x40000468 C   FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
0x40000468 C   FIELD 16w04 TI3SEL (rw): TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved
0x40001000 A PERIPHERAL TIM6
0x40001000 B  REGISTER CR1 (rw): control register 1
0x40001000 C   FIELD 00w01 CEN (rw): Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40001000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40001000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40001000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40001000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40001000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40001004 B  REGISTER CR2 (rw): control register 2
0x40001004 C   FIELD 04w03 MMS (rw): Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x4000100C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000100C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000100C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40001010 B  REGISTER SR (rw): status register
0x40001010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.
0x40001014 B  REGISTER EGR (wo): event generation register
0x40001014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40001024 B  REGISTER CNT (rw): counter
0x40001024 C   FIELD 00w16 CNT (rw): Counter value
0x40001024 C   FIELD 31w01 UIFCPY (ro): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
0x40001028 B  REGISTER PSC (rw): prescaler
0x40001028 C   FIELD 00w16 PSC: Prescaler value
0x4000102C B  REGISTER ARR (rw): auto-reload register
0x4000102C C   FIELD 00w16 ARR: Prescaler value
0x40001400 A PERIPHERAL TIM7
0x40001400 B  REGISTER CR1 (rw): control register 1
0x40001400 C   FIELD 00w01 CEN (rw): Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40001400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40001400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40001400 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40001400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40001400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40001404 B  REGISTER CR2 (rw): control register 2
0x40001404 C   FIELD 04w03 MMS (rw): Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x4000140C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000140C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000140C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40001410 B  REGISTER SR (rw): status register
0x40001410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.
0x40001414 B  REGISTER EGR (wo): event generation register
0x40001414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40001424 B  REGISTER CNT (rw): counter
0x40001424 C   FIELD 00w16 CNT (rw): Counter value
0x40001424 C   FIELD 31w01 UIFCPY (ro): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
0x40001428 B  REGISTER PSC (rw): prescaler
0x40001428 C   FIELD 00w16 PSC: Prescaler value
0x4000142C B  REGISTER ARR (rw): auto-reload register
0x4000142C C   FIELD 00w16 ARR: Prescaler value
0x40002000 A PERIPHERAL TIM14
0x40002000 B  REGISTER CR1 (rw): control register 1
0x40002000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40002000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
0x40002000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
0x40002000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40002000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40002000 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
0x40002000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x4000200C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000200C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000200C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40002010 B  REGISTER SR (rw): status register
0x40002010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
0x40002010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40002010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40002014 B  REGISTER EGR (wo): event generation register
0x40002014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40002014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40002018 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40002018 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40002018 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40002018 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40002018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40002018 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40002018 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40002018 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40002020 B  REGISTER CCER (rw): capture/compare enable register
0x40002020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40002020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40002020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40002024 B  REGISTER CNT (rw): counter
0x40002024 C   FIELD 00w16 CNT: low counter value
0x40002024 C   FIELD 31w01 UIFCPY: UIF Copy
0x40002028 B  REGISTER PSC (rw): prescaler
0x40002028 C   FIELD 00w16 PSC: Prescaler value
0x4000202C B  REGISTER ARR (rw): auto-reload register
0x4000202C C   FIELD 00w16 ARR: Low Auto-reload value
0x40002034 B  REGISTER CCR1 (rw): capture/compare register
0x40002034 C   FIELD 00w16 CCR: Capture/Compare value
0x40002068 B  REGISTER TISEL (rw): TIM timer input selection register
0x40002068 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40002C00 A PERIPHERAL WWDG
0x40002C00 B  REGISTER CR (rw): Control register
0x40002C00 C   FIELD 00w07 T (rw): 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
0x40002C00 C   FIELD 07w01 WDGA (rw): Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGAÂ =Â 1, the watchdog can generate a reset.
0x40002C04 B  REGISTER CFR (rw): Configuration register
0x40002C04 C   FIELD 00w07 W (rw): 7-bit window value These bits contain the window value to be compared with the down-counter.
0x40002C04 C   FIELD 09w01 EWI (rw): Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
0x40002C04 C   FIELD 11w03 WDGTB: Timer base The timebase of the prescaler can be modified as follows:
0x40002C08 B  REGISTER SR (rw): Status register
0x40002C08 C   FIELD 00w01 EWIF: Early wakeup interrupt flag
0x40003000 A PERIPHERAL IWDG
0x40003000 B  REGISTER KR (wo): Key register
0x40003000 C   FIELD 00w16 KEY: Key value (write only, read 0x0000)
0x40003004 B  REGISTER PR (rw): Prescaler register
0x40003004 C   FIELD 00w03 PR (rw): Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
0x40003008 B  REGISTER RLR (rw): Reload register
0x40003008 C   FIELD 00w12 RL: Watchdog counter reload value
0x4000300C B  REGISTER SR (ro): Status register
0x4000300C C   FIELD 00w01 PVU (ro): Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
0x4000300C C   FIELD 01w01 RVU (ro): Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
0x4000300C C   FIELD 02w01 WVU (ro): Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
0x40003010 B  REGISTER WINR (rw): Window register
0x40003010 C   FIELD 00w12 WIN: Watchdog counter window value
0x40004400 A PERIPHERAL USART2
0x40004400 B  REGISTER CR1 (rw): Control register 1
0x40004400 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0x40004400 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40004400 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40004400 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 05w01 RXFNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 07w01 TXFNFIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004400 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004400 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004400 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40004400 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40004400 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40004400 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40004400 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40004400 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40004400 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40004404 B  REGISTER CR2 (rw): Control register 2
0x40004404 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40004404 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40004404 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40004404 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 24w08 ADD (rw): Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0).
0x40004408 B  REGISTER CR3 (rw): Control register 3
0x40004408 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).
0x40004408 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40004408 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40004408 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40004408 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40004408 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data
0x40004408 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40004408 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40004408 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40004408 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40004408 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40004408 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4000440C B  REGISTER BRR (rw): Baud rate register
0x4000440C C   FIELD 00w16 BRR (rw): USART baud rate
0x40004410 B  REGISTER GTPR (rw): Guard time and prescaler register
0x40004410 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to .
0x40004410 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004414 B  REGISTER RTOR (rw): Receiver timeout register
0x40004414 C   FIELD 00w24 RTO: Receiver timeout value
0x40004414 C   FIELD 24w08 BLEN: Block Length
0x40004418 B  REGISTER RQR (wo): Request register
0x40004418 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004418 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40004418 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40004418 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40004418 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4000441C B  REGISTER ISR (ro): Interrupt & status register
0x4000441C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000441C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
0x4000441C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register.
0x4000441C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4000441C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4000441C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000441C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
0x4000441C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000441C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
0x4000441C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register.
0x4000441C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register.
0x4000441C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835.
0x4000441C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4000441C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register.
0x40004420 B  REGISTER ICR (wo): Interrupt flag clear register
0x40004420 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40004420 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40004420 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40004420 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40004420 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40004420 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40004420 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40004420 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40004420 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40004420 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40004420 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40004420 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40004424 B  REGISTER RDR (ro): Receive data register
0x40004424 C   FIELD 00w09 RDR: Receive data value
0x40004428 B  REGISTER TDR (rw): Transmit data register
0x40004428 C   FIELD 00w09 TDR: Transmit data value
0x4000442C B  REGISTER PRESC (rw): Prescaler register
0x4000442C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40005400 A PERIPHERAL I2C1
0x40005400 B  REGISTER CR1 (rw): Control register 1
0x40005400 C   FIELD 00w01 PE (rw): Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0x40005400 C   FIELD 01w01 TXIE (rw): TX Interrupt enable
0x40005400 C   FIELD 02w01 RXIE (rw): RX Interrupt enable
0x40005400 C   FIELD 03w01 ADDRIE (rw): Address match Interrupt enable (slave only)
0x40005400 C   FIELD 04w01 NACKIE (rw): Not acknowledge received Interrupt enable
0x40005400 C   FIELD 05w01 STOPIE (rw): Stop detection Interrupt enable
0x40005400 C   FIELD 06w01 TCIE (rw): Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
0x40005400 C   FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
0x40005400 C   FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005400 C   FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005400 C   FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005400 C   FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 18w01 WUPEN (rw): Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’
0x40005400 C   FIELD 19w01 GCEN (rw): General call enable
0x40005400 C   FIELD 20w01 SMBHEN (rw): SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005400 C   FIELD 21w01 SMBDEN (rw): SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005400 C   FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005400 C   FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005404 B  REGISTER CR2 (rw): Control register 2
0x40005404 C   FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
0x40005404 C   FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect.
0x40005404 C   FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
0x40005404 C   FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005404 C   FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005404 C   FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005408 B  REGISTER OAR1 (rw): Own address register 1
0x40005408 C   FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0x40005408 C   FIELD 10w01 OA1MODE (rw): Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
0x40005408 C   FIELD 15w01 OA1EN (rw): Own Address 1 enable
0x4000540C B  REGISTER OAR2 (rw): Own address register 2
0x4000540C C   FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
0x4000540C C   FIELD 08w03 OA2MSK (rw): Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
0x4000540C C   FIELD 15w01 OA2EN (rw): Own Address 2 enable
0x40005410 B  REGISTER TIMINGR (rw): Timing register
0x40005410 C   FIELD 00w08 SCLL: SCL low period (master mode)
0x40005410 C   FIELD 08w08 SCLH: SCL high period (master mode)
0x40005410 C   FIELD 16w04 SDADEL: Data hold time
0x40005410 C   FIELD 20w04 SCLDEL: Data setup time
0x40005410 C   FIELD 28w04 PRESC: Timing prescaler
0x40005414 B  REGISTER TIMEOUTR (rw): Status register 1
0x40005414 C   FIELD 00w12 TIMEOUTA (rw): Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005414 C   FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
0x40005414 C   FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005418 B  REGISTER ISR: Interrupt and Status register
0x40005418 C   FIELD 00w01 TXE (rw): Transmit data register empty (transmitters)
0x40005418 C   FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters)
0x40005418 C   FIELD 02w01 RXNE (ro): Receive data register not empty (receivers)
0x40005418 C   FIELD 03w01 ADDR (ro): Address matched (slave mode)
0x40005418 C   FIELD 04w01 NACKF (ro): Not acknowledge received flag
0x40005418 C   FIELD 05w01 STOPF (ro): Stop detection flag
0x40005418 C   FIELD 06w01 TC (ro): Transfer Complete (master mode)
0x40005418 C   FIELD 07w01 TCR (ro): Transfer Complete Reload
0x40005418 C   FIELD 08w01 BERR (ro): Bus error
0x40005418 C   FIELD 09w01 ARLO (ro): Arbitration lost
0x40005418 C   FIELD 10w01 OVR (ro): Overrun/Underrun (slave mode)
0x40005418 C   FIELD 11w01 PECERR (ro): PEC Error in reception
0x40005418 C   FIELD 12w01 TIMEOUT (ro): Timeout or t_low detection flag
0x40005418 C   FIELD 13w01 ALERT (ro): SMBus alert
0x40005418 C   FIELD 15w01 BUSY (ro): Bus busy
0x40005418 C   FIELD 16w01 DIR (ro): Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
0x40005418 C   FIELD 17w07 ADDCODE (ro): Address match code (Slave mode)
0x4000541C B  REGISTER ICR (wo): Interrupt clear register
0x4000541C C   FIELD 03w01 ADDRCF: Address Matched flag clear
0x4000541C C   FIELD 04w01 NACKCF: Not Acknowledge flag clear
0x4000541C C   FIELD 05w01 STOPCF: Stop detection flag clear
0x4000541C C   FIELD 08w01 BERRCF: Bus error flag clear
0x4000541C C   FIELD 09w01 ARLOCF: Arbitration lost flag clear
0x4000541C C   FIELD 10w01 OVRCF: Overrun/Underrun flag clear
0x4000541C C   FIELD 11w01 PECCF: PEC Error flag clear
0x4000541C C   FIELD 12w01 TIMOUTCF: Timeout detection flag clear
0x4000541C C   FIELD 13w01 ALERTCF: Alert flag clear
0x40005420 B  REGISTER PECR (ro): PEC register
0x40005420 C   FIELD 00w08 PEC: Packet error checking register
0x40005424 B  REGISTER RXDR (ro): Receive data register
0x40005424 C   FIELD 00w08 RXDATA: 8-bit receive data
0x40005428 B  REGISTER TXDR (rw): Transmit data register
0x40005428 C   FIELD 00w08 TXDATA: 8-bit transmit data
0x40005800 A PERIPHERAL I2C2
0x40005800 B  REGISTER CR1 (rw): Control register 1
0x40005800 C   FIELD 00w01 PE (rw): Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0x40005800 C   FIELD 01w01 TXIE (rw): TX Interrupt enable
0x40005800 C   FIELD 02w01 RXIE (rw): RX Interrupt enable
0x40005800 C   FIELD 03w01 ADDRIE (rw): Address match Interrupt enable (slave only)
0x40005800 C   FIELD 04w01 NACKIE (rw): Not acknowledge received Interrupt enable
0x40005800 C   FIELD 05w01 STOPIE (rw): Stop detection Interrupt enable
0x40005800 C   FIELD 06w01 TCIE (rw): Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
0x40005800 C   FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
0x40005800 C   FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005800 C   FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005800 C   FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005800 C   FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 18w01 WUPEN (rw): Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to . Note: WUPEN can be set only when DNF = '0000’
0x40005800 C   FIELD 19w01 GCEN (rw): General call enable
0x40005800 C   FIELD 20w01 SMBHEN (rw): SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005800 C   FIELD 21w01 SMBDEN (rw): SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005800 C   FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005800 C   FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005804 B  REGISTER CR2 (rw): Control register 2
0x40005804 C   FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C   FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
0x40005804 C   FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0’ to this bit has no effect.
0x40005804 C   FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
0x40005804 C   FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C   FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005804 C   FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005804 C   FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0’. Refer to .
0x40005808 B  REGISTER OAR1 (rw): Own address register 1
0x40005808 C   FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0x40005808 C   FIELD 10w01 OA1MODE (rw): Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
0x40005808 C   FIELD 15w01 OA1EN (rw): Own Address 1 enable
0x4000580C B  REGISTER OAR2 (rw): Own address register 2
0x4000580C C   FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
0x4000580C C   FIELD 08w03 OA2MSK (rw): Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
0x4000580C C   FIELD 15w01 OA2EN (rw): Own Address 2 enable
0x40005810 B  REGISTER TIMINGR (rw): Timing register
0x40005810 C   FIELD 00w08 SCLL: SCL low period (master mode)
0x40005810 C   FIELD 08w08 SCLH: SCL high period (master mode)
0x40005810 C   FIELD 16w04 SDADEL: Data hold time
0x40005810 C   FIELD 20w04 SCLDEL: Data setup time
0x40005810 C   FIELD 28w04 PRESC: Timing prescaler
0x40005814 B  REGISTER TIMEOUTR (rw): Status register 1
0x40005814 C   FIELD 00w12 TIMEOUTA (rw): Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0x40005814 C   FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
0x40005814 C   FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005814 C   FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
0x40005814 C   FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005818 B  REGISTER ISR: Interrupt and Status register
0x40005818 C   FIELD 00w01 TXE (rw): Transmit data register empty (transmitters)
0x40005818 C   FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters)
0x40005818 C   FIELD 02w01 RXNE (ro): Receive data register not empty (receivers)
0x40005818 C   FIELD 03w01 ADDR (ro): Address matched (slave mode)
0x40005818 C   FIELD 04w01 NACKF (ro): Not acknowledge received flag
0x40005818 C   FIELD 05w01 STOPF (ro): Stop detection flag
0x40005818 C   FIELD 06w01 TC (ro): Transfer Complete (master mode)
0x40005818 C   FIELD 07w01 TCR (ro): Transfer Complete Reload
0x40005818 C   FIELD 08w01 BERR (ro): Bus error
0x40005818 C   FIELD 09w01 ARLO (ro): Arbitration lost
0x40005818 C   FIELD 10w01 OVR (ro): Overrun/Underrun (slave mode)
0x40005818 C   FIELD 11w01 PECERR (ro): PEC Error in reception
0x40005818 C   FIELD 12w01 TIMEOUT (ro): Timeout or t_low detection flag
0x40005818 C   FIELD 13w01 ALERT (ro): SMBus alert
0x40005818 C   FIELD 15w01 BUSY (ro): Bus busy
0x40005818 C   FIELD 16w01 DIR (ro): Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
0x40005818 C   FIELD 17w07 ADDCODE (ro): Address match code (Slave mode)
0x4000581C B  REGISTER ICR (wo): Interrupt clear register
0x4000581C C   FIELD 03w01 ADDRCF: Address Matched flag clear
0x4000581C C   FIELD 04w01 NACKCF: Not Acknowledge flag clear
0x4000581C C   FIELD 05w01 STOPCF: Stop detection flag clear
0x4000581C C   FIELD 08w01 BERRCF: Bus error flag clear
0x4000581C C   FIELD 09w01 ARLOCF: Arbitration lost flag clear
0x4000581C C   FIELD 10w01 OVRCF: Overrun/Underrun flag clear
0x4000581C C   FIELD 11w01 PECCF: PEC Error flag clear
0x4000581C C   FIELD 12w01 TIMOUTCF: Timeout detection flag clear
0x4000581C C   FIELD 13w01 ALERTCF: Alert flag clear
0x40005820 B  REGISTER PECR (ro): PEC register
0x40005820 C   FIELD 00w08 PEC: Packet error checking register
0x40005824 B  REGISTER RXDR (ro): Receive data register
0x40005824 C   FIELD 00w08 RXDATA: 8-bit receive data
0x40005828 B  REGISTER TXDR (rw): Transmit data register
0x40005828 C   FIELD 00w08 TXDATA: 8-bit transmit data
0x40012400 A PERIPHERAL ADC
0x40012400 B  REGISTER ISR (rw): ADC interrupt and status register
0x40012400 C   FIELD 00w01 ADRDY (rw): ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 01w01 EOSMP (rw): End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1’.
0x40012400 C   FIELD 02w01 EOC (rw): End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
0x40012400 C   FIELD 03w01 EOS (rw): End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 04w01 OVR (rw): ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 07w01 AWD1 (rw): Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1.
0x40012400 C   FIELD 08w01 AWD2 (rw): Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
0x40012400 C   FIELD 09w01 AWD3 (rw): Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
0x40012400 C   FIELD 11w01 EOCAL (rw): End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 13w01 CCRDY (rw): Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
0x40012404 B  REGISTER IER (rw): ADC interrupt enable register
0x40012404 C   FIELD 00w01 ADRDYIE (rw): ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 01w01 EOSMPIE (rw): End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 02w01 EOCIE (rw): End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 03w01 EOSIE (rw): End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 04w01 OVRIE (rw): Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 07w01 AWD1IE (rw): Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 08w01 AWD2IE (rw): Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 09w01 AWD3IE (rw): Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 11w01 EOCALIE (rw): End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 13w01 CCRDYIE (rw): Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012408 B  REGISTER CR (rw): ADC control register
0x40012408 C   FIELD 00w01 ADEN (rw): ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)
0x40012408 C   FIELD 01w01 ADDIS (rw): ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)
0x40012408 C   FIELD 02w01 ADSTART (rw): ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
0x40012408 C   FIELD 04w01 ADSTP (rw): ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
0x40012408 C   FIELD 28w01 ADVREGEN (rw): ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
0x40012408 C   FIELD 31w01 ADCAL (rw): ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing).
0x4001240C B  REGISTER CFGR1 (rw): ADC configuration register 1
0x4001240C C   FIELD 00w01 DMAEN (rw): Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 01w01 DMACFG (rw): Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 391 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 02w01 SCANDIR (rw): Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 03w02 RES (rw): Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADENÂ =Â 0.
0x4001240C C   FIELD 05w01 ALIGN (rw): Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 389 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 06w03 EXTSEL (rw): External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 10w02 EXTEN (rw): External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 12w01 OVRMOD (rw): Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 13w01 CONT (rw): Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 14w01 WAIT (rw): Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 15w01 AUTOFF (rw): Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 16w01 DISCEN (rw): Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 21w01 CHSELRMOD (rw): Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 22w01 AWD1SGL (rw): Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 23w01 AWD1EN (rw): Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 26w05 AWD1CH (rw): Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 B  REGISTER CFGR2 (rw): ADC configuration register 2
0x40012410 C   FIELD 00w01 OVSE (rw): Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 02w03 OVSR (rw): Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 05w04 OVSS (rw): Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 09w01 TOVS (rw): Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 29w01 LFTRIG (rw): Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 C   FIELD 30w02 CKMODE (rw): ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
0x40012414 B  REGISTER SMPR (rw): ADC sampling time register
0x40012414 C   FIELD 00w03 SMP1 (rw): Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 04w03 SMP2 (rw): Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 08w01 SMPSEL0 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 09w01 SMPSEL1 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 10w01 SMPSEL2 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 11w01 SMPSEL3 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 12w01 SMPSEL4 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 13w01 SMPSEL5 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 14w01 SMPSEL6 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 15w01 SMPSEL7 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 16w01 SMPSEL8 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 17w01 SMPSEL9 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 18w01 SMPSEL10 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 19w01 SMPSEL11 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 20w01 SMPSEL12 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 21w01 SMPSEL13 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 22w01 SMPSEL14 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 23w01 SMPSEL15 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 24w01 SMPSEL16 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 25w01 SMPSEL17 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012414 C   FIELD 26w01 SMPSEL18 (rw): Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012420 B  REGISTER AWD1TR (rw): ADC watchdog threshold register
0x40012420 C   FIELD 00w12 LT1 (rw): Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x40012420 C   FIELD 16w12 HT1 (rw): Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x40012424 B  REGISTER AWD2TR (rw): ADC watchdog threshold register
0x40012424 C   FIELD 00w12 LT2 (rw): Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x40012424 C   FIELD 16w12 HT2 (rw): Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x40012428 B  REGISTER CHSELR0 (rw): ADC channel selection register
0x40012428 B  REGISTER CHSELR1 (rw): ADC channel selection register
0x40012428 C   FIELD 00w01 CHSEL0 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 00w04 SQ1 (rw): 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 01w01 CHSEL1 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 02w01 CHSEL2 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 03w01 CHSEL3 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 04w01 CHSEL4 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 04w04 SQ2 (rw): 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 05w01 CHSEL5 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 06w01 CHSEL6 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 07w01 CHSEL7 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 08w01 CHSEL8 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 08w04 SQ3 (rw): 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 09w01 CHSEL9 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 10w01 CHSEL10 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 11w01 CHSEL11 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 12w01 CHSEL12 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 12w04 SQ4 (rw): 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 13w01 CHSEL13 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 14w01 CHSEL14 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 15w01 CHSEL15 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 16w01 CHSEL16 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 16w04 SQ5 (rw): 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 17w01 CHSEL17 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 18w01 CHSEL18 (rw): Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x40012428 C   FIELD 20w04 SQ6 (rw): 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 24w04 SQ7 (rw): 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012428 C   FIELD 28w04 SQ8 (rw): 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x4001242C B  REGISTER AWD3TR (rw): ADC watchdog threshold register
0x4001242C C   FIELD 00w12 LT3 (rw): Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x4001242C C   FIELD 16w12 HT3 (rw): Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395.
0x40012440 B  REGISTER DR (ro): ADC data register
0x40012440 C   FIELD 00w16 DATA (ro): Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 389. Just after a calibration is complete, DATA[6:0] contains the calibration factor.
0x400124A0 B  REGISTER AWD2CR (rw): ADC Analog Watchdog 2 Configuration register
0x400124A0 C   FIELD 00w01 AWD2CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 01w01 AWD2CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 02w01 AWD2CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 03w01 AWD2CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 04w01 AWD2CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 05w01 AWD2CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 06w01 AWD2CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 07w01 AWD2CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 08w01 AWD2CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 09w01 AWD2CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 10w01 AWD2CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 11w01 AWD2CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 12w01 AWD2CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 13w01 AWD2CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 14w01 AWD2CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 15w01 AWD2CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 16w01 AWD2CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 17w01 AWD2CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 18w01 AWD2CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x400124A4 B  REGISTER AWD3CR (rw): ADC Analog Watchdog 3 Configuration register
0x400124A4 C   FIELD 00w01 AWD3CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 01w01 AWD3CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 02w01 AWD3CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 03w01 AWD3CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 04w01 AWD3CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 05w01 AWD3CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 06w01 AWD3CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 07w01 AWD3CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 08w01 AWD3CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 09w01 AWD3CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 10w01 AWD3CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 11w01 AWD3CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 12w01 AWD3CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 13w01 AWD3CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 14w01 AWD3CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 15w01 AWD3CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 16w01 AWD3CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 17w01 AWD3CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 18w01 AWD3CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124B4 B  REGISTER CALFACT (rw): ADC Calibration factor
0x400124B4 C   FIELD 00w07 CALFACT (rw): Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.
0x40012708 B  REGISTER CCR (rw): ADC common configuration register
0x40012708 C   FIELD 18w04 PRESC (rw): ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
0x40012708 C   FIELD 22w01 VREFEN (rw): VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012708 C   FIELD 23w01 TSEN (rw): Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
0x40012708 C   FIELD 24w01 VBATEN (rw): VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)
0x40012C00 A PERIPHERAL TIM1
0x40012C00 B  REGISTER CR1 (rw): control register 1
0x40012C00 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40012C00 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40012C00 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40012C00 C   FIELD 03w01 OPM (rw): One pulse mode
0x40012C00 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40012C00 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed
0x40012C00 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40012C00 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
0x40012C00 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40012C04 B  REGISTER CR2 (rw): control register 2
0x40012C04 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40012C04 C   FIELD 04w03 MMS (rw): Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C04 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40012C04 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40012C04 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x40012C04 C   FIELD 10w01 OIS2 (rw): Output Idle state (OC2 output)
0x40012C04 C   FIELD 11w01 OIS2N (rw): Output Idle state (OC2N output)
0x40012C04 C   FIELD 12w01 OIS3 (rw): Output Idle state (OC3 output)
0x40012C04 C   FIELD 13w01 OIS3N (rw): Output Idle state (OC3N output)
0x40012C04 C   FIELD 14w01 OIS4 (rw): Output Idle state (OC4 output)
0x40012C04 C   FIELD 16w01 OIS5 (rw): Output Idle state (OC5 output)
0x40012C04 C   FIELD 18w01 OIS6 (rw): Output Idle state (OC6 output)
0x40012C04 C   FIELD 20w04 MMS2 (rw): Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 B  REGISTER SMCR (rw): slave mode control register
0x40012C08 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source.
0x40012C08 C   FIELD 04w03 TS1 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C08 C   FIELD 07w01 MSM (rw): Master/slave mode
0x40012C08 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40012C08 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40012C08 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40012C08 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40012C08 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C0C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x40012C0C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x40012C0C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40012C0C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x40012C0C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x40012C0C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x40012C0C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x40012C0C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x40012C0C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x40012C0C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40012C0C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40012C0C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x40012C0C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x40012C0C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x40012C0C C   FIELD 13w01 COMDE (rw): COM DMA request enable
0x40012C0C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40012C10 B  REGISTER SR (rw): status register
0x40012C10 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40012C10 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40012C10 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40012C10 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40012C10 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40012C10 C   FIELD 05w01 COMIF (rw): COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software.
0x40012C10 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40012C10 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40012C10 C   FIELD 08w01 B2IF (rw): Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
0x40012C10 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40012C10 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40012C10 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40012C10 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40012C10 C   FIELD 13w01 SBIF (rw): System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
0x40012C10 C   FIELD 16w01 CC5IF (rw): Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)
0x40012C10 C   FIELD 17w01 CC6IF (rw): Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)
0x40012C14 B  REGISTER EGR (wo): event generation register
0x40012C14 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40012C14 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40012C14 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40012C14 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40012C14 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40012C14 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
0x40012C14 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 08w01 B2G (wo): Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C18 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (output mode)
0x40012C18 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40012C18 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40012C18 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40012C18 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40012C18 C   FIELD 04w03 OC1M1 (rw): Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16.
0x40012C18 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40012C18 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40012C18 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40012C18 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40012C18 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40012C18 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40012C18 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40012C18 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40012C18 C   FIELD 16w01 OC1M2 (rw): Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16.
0x40012C18 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x40012C1C B  REGISTER CCMR2_Input (rw): capture/compare mode register 2 (output mode)
0x40012C1C B  REGISTER CCMR2_Output (rw): capture/compare mode register 2 (output mode)
0x40012C1C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection
0x40012C1C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection
0x40012C1C C   FIELD 02w01 OC3FE (rw): Output compare 3 fast enable
0x40012C1C C   FIELD 02w02 IC3PSC (rw): Input capture 3 prescaler
0x40012C1C C   FIELD 03w01 OC3PE (rw): Output compare 3 preload enable
0x40012C1C C   FIELD 04w03 OC3M (rw): Output compare 3 mode
0x40012C1C C   FIELD 04w04 IC3F (rw): Input capture 3 filter
0x40012C1C C   FIELD 07w01 OC3CE (rw): Output compare 3 clear enable
0x40012C1C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection
0x40012C1C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection
0x40012C1C C   FIELD 10w01 OC4FE (rw): Output compare 4 fast enable
0x40012C1C C   FIELD 10w02 IC4PSC (rw): Input capture 4 prescaler
0x40012C1C C   FIELD 11w01 OC4PE (rw): Output compare 4 preload enable
0x40012C1C C   FIELD 12w03 OC4M (rw): Output compare 4 mode
0x40012C1C C   FIELD 12w04 IC4F (rw): Input capture 4 filter
0x40012C1C C   FIELD 15w01 OC4CE (rw): Output compare 4 clear enable
0x40012C1C C   FIELD 16w01 OC3M_3 (rw): Output compare 3 mode, bit 3
0x40012C1C C   FIELD 24w01 OC4M_3 (rw): Output compare 4 mode, bit 3
0x40012C20 B  REGISTER CCER (rw): capture/compare enable register
0x40012C20 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40012C20 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40012C20 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40012C20 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 06w01 CC2NE (rw): Capture/Compare 2 complementary output enable
0x40012C20 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40012C20 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 10w01 CC3NE (rw): Capture/Compare 3 complementary output enable
0x40012C20 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40012C20 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 16w01 CC5E (rw): Capture/Compare 5 output enable
0x40012C20 C   FIELD 17w01 CC5P (rw): Capture/Compare 5 output Polarity
0x40012C20 C   FIELD 20w01 CC6E (rw): Capture/Compare 6 output enable
0x40012C20 C   FIELD 21w01 CC6P (rw): Capture/Compare 6 output Polarity
0x40012C24 B  REGISTER CNT: counter
0x40012C24 C   FIELD 00w16 CNT (rw): Counter value
0x40012C24 C   FIELD 31w01 UIFCPY (ro): UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
0x40012C28 B  REGISTER PSC (rw): prescaler
0x40012C28 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
0x40012C2C B  REGISTER ARR (rw): auto-reload register
0x40012C2C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40012C30 B  REGISTER RCR (rw): repetition counter register
0x40012C30 C   FIELD 00w16 REP: Repetition counter value
0x40012C34 B  REGISTER CCR1 (rw): capture/compare register
0x40012C34 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C38 B  REGISTER CCR2 (rw): capture/compare register
0x40012C38 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C3C B  REGISTER CCR3 (rw): capture/compare register
0x40012C3C C   FIELD 00w16 CCR: Capture/Compare value
0x40012C40 B  REGISTER CCR4 (rw): capture/compare register
0x40012C40 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C44 B  REGISTER BDTR (rw): break and dead-time register
0x40012C44 C   FIELD 00w08 DTG (rw): Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40012C44 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 12w01 BKE (rw): Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A).
0x40012C44 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 20w04 BK2F (rw): Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 24w01 BK2E (rw): Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 25w01 BK2P (rw): Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 27w01 BK2DSRM (rw): Break2 Disarm Refer to BKDSRM description
0x40012C44 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 29w01 BK2BID (rw): Break2 bidirectional Refer to BKBID description
0x40012C48 B  REGISTER DCR (rw): DMA control register
0x40012C48 C   FIELD 00w05 DBA (rw): DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0x40012C48 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.
0x40012C4C B  REGISTER DMAR (rw): DMA address for full transfer
0x40012C4C C   FIELD 00w32 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40012C54 B  REGISTER CCMR3_Output (rw): capture/compare mode register 2 (output mode)
0x40012C54 C   FIELD 02w01 OC5FE: Output compare 5 fast enable
0x40012C54 C   FIELD 03w01 OC5PE: Output compare 5 preload enable
0x40012C54 C   FIELD 04w03 OC5M: Output compare 5 mode
0x40012C54 C   FIELD 07w01 OC5CE: Output compare 5 clear enable
0x40012C54 C   FIELD 10w01 OC6FE: Output compare 6 fast enable
0x40012C54 C   FIELD 11w01 OC6PE: Output compare 6 preload enable
0x40012C54 C   FIELD 12w03 OC6M: Output compare 6 mode
0x40012C54 C   FIELD 15w01 OC6CE: Output compare 6 clear enable
0x40012C54 C   FIELD 16w01 OC5M_3: Output compare 5 mode, bit 3
0x40012C54 C   FIELD 24w01 OC6M_3: Output compare 6 mode, bit 3
0x40012C58 B  REGISTER CCR5 (rw): capture/compare register
0x40012C58 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C58 C   FIELD 29w01 GC5C1 (rw): Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 30w01 GC5C2 (rw): Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 31w01 GC5C3 (rw): Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C5C B  REGISTER CCR6 (rw): capture/compare register
0x40012C5C C   FIELD 00w16 CCR: Capture/Compare value
0x40012C60 B  REGISTER AF1 (rw): TIM1 alternate function option register 1
0x40012C60 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 B  REGISTER AF2 (rw): TIM1 alternate function option register 2
0x40012C64 C   FIELD 00w01 BK2INE (rw): BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is 'ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 09w01 BK2INP (rw): BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C68 B  REGISTER TISEL (rw): TIM1 timer input selection register
0x40012C68 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40012C68 C   FIELD 08w04 TI2SEL (rw): selects TI2[0] to TI2[15] input Others: Reserved
0x40012C68 C   FIELD 16w04 TI3SEL (rw): selects TI3[0] to TI3[15] input Others: Reserved
0x40012C68 C   FIELD 24w04 TI4SEL (rw): selects TI4[0] to TI4[15] input Others: Reserved
0x40013800 A PERIPHERAL USART1
0x40013800 B  REGISTER CR1 (rw): Control register 1
0x40013800 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0x40013800 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40013800 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0’ followed by '1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40013800 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 05w01 RXFNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 07w01 TXFNFIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013800 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013800 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013800 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40013800 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40013800 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40013800 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40013800 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40013800 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40013800 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40013804 B  REGISTER CR2 (rw): Control register 2
0x40013804 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40013804 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40013804 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0).
0x40013804 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 24w08 ADD (rw): Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0).
0x40013808 B  REGISTER CR3 (rw): Control register 3
0x40013808 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).
0x40013808 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40013808 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40013808 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40013808 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).
0x40013808 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data
0x40013808 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40013808 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40013808 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40013808 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40013808 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40013808 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4001380C B  REGISTER BRR (rw): Baud rate register
0x4001380C C   FIELD 00w16 BRR (rw): USART baud rate
0x40013810 B  REGISTER GTPR (rw): Guard time and prescaler register
0x40013810 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010 0000: Divides the source clock by 32 (IrDA mode) ... 1111 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0’ when the Smartcard and IrDA modes are not supported. Refer to .
0x40013810 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013814 B  REGISTER RTOR (rw): Receiver timeout register
0x40013814 C   FIELD 00w24 RTO: Receiver timeout value
0x40013814 C   FIELD 24w08 BLEN: Block Length
0x40013818 B  REGISTER RQR (wo): Request register
0x40013818 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013818 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40013818 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40013818 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40013818 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing '1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4001381C B  REGISTER ISR (ro): Interrupt & status register
0x4001381C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4001381C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set.
0x4001381C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register.
0x4001381C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4001381C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4001381C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4001381C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register.
0x4001381C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4001381C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period.
0x4001381C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register.
0x4001381C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register.
0x4001381C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1’. Refer to on page 835.
0x4001381C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4001381C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register.
0x40013820 B  REGISTER ICR (wo): Interrupt flag clear register
0x40013820 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40013820 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40013820 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40013820 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40013820 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40013820 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40013820 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40013820 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40013820 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40013820 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40013820 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40013820 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.
0x40013824 B  REGISTER RDR (ro): Receive data register
0x40013824 C   FIELD 00w09 RDR: Receive data value
0x40013828 B  REGISTER TDR (rw): Transmit data register
0x40013828 C   FIELD 00w09 TDR: Transmit data value
0x4001382C B  REGISTER PRESC (rw): Prescaler register
0x4001382C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40014000 A PERIPHERAL TIM15
0x40014000 B  REGISTER CR1 (rw): control register 1
0x40014000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40014000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014000 C   FIELD 08w02 CKD (rw): Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
0x40014000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014004 B  REGISTER CR2 (rw): control register 2
0x40014004 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014004 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014004 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014004 C   FIELD 04w03 MMS (rw): Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
0x40014004 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40014004 C   FIELD 08w01 OIS1 (rw): Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
0x40014004 C   FIELD 09w01 OIS1N (rw): Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
0x40014004 C   FIELD 10w01 OIS2 (rw): Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
0x40014008 B  REGISTER SMCR (rw): slave mode control register
0x40014008 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40014008 C   FIELD 04w03 TS1 (rw): Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40014008 C   FIELD 07w01 MSM (rw): Master/slave mode
0x40014008 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40014008 C   FIELD 20w02 TS2 (rw): Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4001400C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001400C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001400C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001400C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4001400C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001400C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4001400C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001400C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001400C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4001400C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4001400C C   FIELD 13w01 COMDE (rw): COM DMA request enable
0x4001400C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40014010 B  REGISTER SR (rw): status register
0x40014010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014010 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40014010 C   FIELD 05w01 COMIF (rw): COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.
0x40014010 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40014010 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014010 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40014014 B  REGISTER EGR (wo): event generation register
0x40014014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014014 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40014014 C   FIELD 05w01 COMG (rw): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014014 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014014 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014018 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014018 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014018 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014018 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014018 C   FIELD 04w03 OC1M1 (rw): Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
0x40014018 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014018 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40014018 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40014018 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40014018 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40014018 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40014018 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40014018 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40014018 C   FIELD 16w01 OC1M2 (rw): Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.
0x40014018 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x40014020 B  REGISTER CCER (rw): capture/compare enable register
0x40014020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014020 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014020 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40014020 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40014020 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40014024 B  REGISTER CNT: counter
0x40014024 C   FIELD 00w16 CNT (rw): counter value
0x40014024 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014028 B  REGISTER PSC (rw): prescaler
0x40014028 C   FIELD 00w16 PSC: Prescaler value
0x4001402C B  REGISTER ARR (rw): auto-reload register
0x4001402C C   FIELD 00w16 ARR: Auto-reload value
0x40014030 B  REGISTER RCR (rw): repetition counter register
0x40014030 C   FIELD 00w08 REP: Repetition counter value
0x40014034 B  REGISTER CCR1 (rw): capture/compare register
0x40014034 C   FIELD 00w16 CCR: Capture/Compare value
0x40014038 B  REGISTER CCR2 (rw): capture/compare register
0x40014038 C   FIELD 00w16 CCR: Capture/Compare value
0x40014044 B  REGISTER BDTR (rw): break and dead-time register
0x40014044 C   FIELD 00w08 DTG (rw): Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014044 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
0x40014044 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014048 B  REGISTER DCR (rw): DMA control register
0x40014048 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0x40014048 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4001404C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001404C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014060 B  REGISTER AF1 (rw): TIM15 alternate register 1
0x40014060 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014068 B  REGISTER TISEL (rw): input selection register
0x40014068 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40014068 C   FIELD 08w04 TI2SEL (rw): selects TI2[0] to TI2[15] input Others: Reserved
0x40014400 A PERIPHERAL TIM16
0x40014400 B  REGISTER CR1 (rw): control register 1
0x40014400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014400 C   FIELD 03w01 OPM (rw): One pulse mode
0x40014400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
0x40014400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014404 B  REGISTER CR2 (rw): control register 2
0x40014404 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014404 C   FIELD 08w01 OIS1 (rw): Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014404 C   FIELD 09w01 OIS1N (rw): Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x4001440C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001440C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001440C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001440C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001440C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001440C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001440C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40014410 B  REGISTER SR (rw): status register
0x40014410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014410 C   FIELD 05w01 COMIF (rw): COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.
0x40014410 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014414 B  REGISTER EGR (wo): event generation register
0x40014414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014414 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014414 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014418 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014418 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014418 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014418 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014418 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014418 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014420 B  REGISTER CCER (rw): capture/compare enable register
0x40014420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014420 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014424 B  REGISTER CNT: counter
0x40014424 C   FIELD 00w16 CNT (rw): counter value
0x40014424 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014428 B  REGISTER PSC (rw): prescaler
0x40014428 C   FIELD 00w16 PSC: Prescaler value
0x4001442C B  REGISTER ARR (rw): auto-reload register
0x4001442C C   FIELD 00w16 ARR: Auto-reload value
0x40014430 B  REGISTER RCR (rw): repetition counter register
0x40014430 C   FIELD 00w08 REP: Repetition counter value
0x40014434 B  REGISTER CCR1 (rw): capture/compare register
0x40014434 C   FIELD 00w16 CCR: Capture/Compare value
0x40014444 B  REGISTER BDTR (rw): break and dead-time register
0x40014444 C   FIELD 00w08 DTG (rw): Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014444 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846).
0x40014444 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014448 B  REGISTER DCR (rw): DMA control register
0x40014448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40014448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
0x4001444C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001444C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014460 B  REGISTER AF1 (rw): TIM17 option register 1
0x40014460 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014468 B  REGISTER TISEL (rw): input selection register
0x40014468 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40014800 A PERIPHERAL TIM17
0x40014800 B  REGISTER CR1 (rw): control register 1
0x40014800 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014800 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014800 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014800 C   FIELD 03w01 OPM (rw): One pulse mode
0x40014800 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014800 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
0x40014800 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014804 B  REGISTER CR2 (rw): control register 2
0x40014804 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014804 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014804 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014804 C   FIELD 08w01 OIS1 (rw): Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014804 C   FIELD 09w01 OIS1N (rw): Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x4001480C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001480C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001480C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001480C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001480C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001480C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001480C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40014810 B  REGISTER SR (rw): status register
0x40014810 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014810 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014810 C   FIELD 05w01 COMIF (rw): COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.
0x40014810 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014810 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014814 B  REGISTER EGR (wo): event generation register
0x40014814 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014814 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014814 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014814 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014818 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014818 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014818 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014818 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014818 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014818 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014818 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014818 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014818 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014818 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014820 B  REGISTER CCER (rw): capture/compare enable register
0x40014820 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014820 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014820 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014820 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014824 B  REGISTER CNT: counter
0x40014824 C   FIELD 00w16 CNT (rw): counter value
0x40014824 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014828 B  REGISTER PSC (rw): prescaler
0x40014828 C   FIELD 00w16 PSC: Prescaler value
0x4001482C B  REGISTER ARR (rw): auto-reload register
0x4001482C C   FIELD 00w16 ARR: Auto-reload value
0x40014830 B  REGISTER RCR (rw): repetition counter register
0x40014830 C   FIELD 00w08 REP: Repetition counter value
0x40014834 B  REGISTER CCR1 (rw): capture/compare register
0x40014834 C   FIELD 00w16 CCR: Capture/Compare value
0x40014844 B  REGISTER BDTR (rw): break and dead-time register
0x40014844 C   FIELD 00w08 DTG (rw): Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014844 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846).
0x40014844 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014848 B  REGISTER DCR (rw): DMA control register
0x40014848 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40014848 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
0x4001484C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001484C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014860 B  REGISTER AF1 (rw): TIM17 option register 1
0x40014860 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is 'ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014868 B  REGISTER TISEL (rw): input selection register
0x40014868 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40015800 A PERIPHERAL DBG
0x40015800 B  REGISTER IDCODE (ro): MCU Device ID Code Register
0x40015800 C   FIELD 00w12 DEV_ID: Device Identifier
0x40015800 C   FIELD 16w16 REV_ID: Revision Identifier
0x40015804 B  REGISTER CR (rw): DBG configuration register
0x40015804 C   FIELD 01w01 DBG_STOP (rw): Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration.
0x40015804 C   FIELD 02w01 DBG_STANDBY (rw): Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.
0x40015808 B  REGISTER APB_FZ1 (rw): DBG APB freeze register 1
0x40015808 C   FIELD 01w01 DBG_TIM3_STOP (rw): Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
0x40015808 C   FIELD 04w01 DBG_TIM6_STOP (rw): Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:
0x40015808 C   FIELD 05w01 DBG_TIM7_STOP (rw): Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
0x40015808 C   FIELD 10w01 DBG_RTC_STOP (rw): Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
0x40015808 C   FIELD 11w01 DBG_WWDG_STOP (rw): Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
0x40015808 C   FIELD 12w01 DBG_IWDG_STOP (rw): Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
0x40015808 C   FIELD 21w01 DBG_I2C1_SMBUS_TIMEOUT (rw): SMBUS timeout when core is halted
0x40015808 C   FIELD 22w01 DBG_I2C2_SMBUS_TIMEOUT (rw): SMBUS timeout when core is halted
0x4001580C B  REGISTER APB_FZ2 (rw): DBG APB freeze register 2
0x4001580C C   FIELD 11w01 DBG_TIM1_STOP (rw): Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0x4001580C C   FIELD 15w01 DBG_TIM14_STOP (rw): Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0x4001580C C   FIELD 16w01 DBG_TIM15_STOP (rw): Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.
0x4001580C C   FIELD 17w01 DBG_TIM16_STOP (rw): Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0x4001580C C   FIELD 18w01 DBG_TIM17_STOP (rw): Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0x40020800 A PERIPHERAL DMAMUX
0x40020800 B  REGISTER CCR0 (rw): DMA Multiplexer Channel 0 Control register
0x40020800 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020800 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020800 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020800 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020800 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020800 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020800 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020804 B  REGISTER CCR1 (rw): DMA Multiplexer Channel 1 Control register
0x40020804 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020804 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020804 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020804 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020804 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020804 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020804 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020808 B  REGISTER CCR2 (rw): DMA Multiplexer Channel 2 Control register
0x40020808 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020808 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020808 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020808 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020808 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020808 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020808 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x4002080C B  REGISTER CCR3 (rw): DMA Multiplexer Channel 3 Control register
0x4002080C C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x4002080C C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x4002080C C   FIELD 09w01 EGE (rw): Event generation enable
0x4002080C C   FIELD 16w01 SE (rw): Synchronization enable
0x4002080C C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x4002080C C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x4002080C C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020810 B  REGISTER CCR4 (rw): DMA Multiplexer Channel 4 Control register
0x40020810 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020810 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020810 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020810 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020810 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020810 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020810 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020814 B  REGISTER CCR5 (rw): DMA Multiplexer Channel 5 Control register
0x40020814 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020814 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020814 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020814 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020814 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020814 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020814 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020818 B  REGISTER CCR6 (rw): DMA Multiplexer Channel 6 Control register
0x40020818 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020818 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020818 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020818 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020818 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020818 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020818 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x4002081C B  REGISTER CCR7 (rw): DMA Multiplexer Channel 7 Control register
0x4002081C C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x4002081C C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x4002081C C   FIELD 09w01 EGE (rw): Event generation enable
0x4002081C C   FIELD 16w01 SE (rw): Synchronization enable
0x4002081C C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x4002081C C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x4002081C C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020820 B  REGISTER CCR8 (rw): DMA Multiplexer Channel 8 Control register
0x40020820 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020820 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020820 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020820 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020820 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020820 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020820 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020824 B  REGISTER CCR9 (rw): DMA Multiplexer Channel 9 Control register
0x40020824 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020824 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020824 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020824 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020824 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020824 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020824 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020828 B  REGISTER CCR10 (rw): DMA Multiplexer Channel 10 Control register
0x40020828 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020828 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020828 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020828 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020828 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020828 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020828 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x4002082C B  REGISTER CCR11 (rw): DMA Multiplexer Channel 11 Control register
0x4002082C C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x4002082C C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x4002082C C   FIELD 09w01 EGE (rw): Event generation enable
0x4002082C C   FIELD 16w01 SE (rw): Synchronization enable
0x4002082C C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x4002082C C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x4002082C C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020880 B  REGISTER CSR (ro): DMAMUX request line multiplexer interrupt channel status register
0x40020880 C   FIELD 00w01 SOF0 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 01w01 SOF1 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 02w01 SOF2 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 03w01 SOF3 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 04w01 SOF4 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 05w01 SOF5 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 06w01 SOF6 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 07w01 SOF7 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 08w01 SOF8 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 09w01 SOF9 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 10w01 SOF10 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020880 C   FIELD 11w01 SOF11 (ro): Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
0x40020884 B  REGISTER CFR (wo): DMAMUX request line multiplexer interrupt clear flag register
0x40020884 C   FIELD 00w01 CSOF0 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 01w01 CSOF1 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 02w01 CSOF2 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 03w01 CSOF3 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 04w01 CSOF4 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 05w01 CSOF5 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 06w01 CSOF6 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 07w01 CSOF7 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 08w01 CSOF8 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 09w01 CSOF9 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 10w01 CSOF10 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020884 C   FIELD 11w01 CSOF11 (wo): Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.
0x40020900 B  REGISTER RGCR0 (rw): DMAMUX request generator channel x configuration register
0x40020900 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020900 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020900 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020900 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020900 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020904 B  REGISTER RGCR1 (rw): DMAMUX request generator channel x configuration register
0x40020904 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020904 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020904 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020904 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020904 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020908 B  REGISTER RGCR2 (rw): DMAMUX request generator channel x configuration register
0x40020908 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020908 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020908 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020908 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020908 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x4002090C B  REGISTER RGCR3 (rw): DMAMUX request generator channel x configuration register
0x4002090C C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x4002090C C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x4002090C C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x4002090C C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x4002090C C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020940 B  REGISTER RGSR (ro): DMAMUX request generator interrupt status register
0x40020940 C   FIELD 00w01 OF0 (ro): Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
0x40020940 C   FIELD 01w01 OF1 (ro): Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
0x40020940 C   FIELD 02w01 OF2 (ro): Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
0x40020940 C   FIELD 03w01 OF3 (ro): Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.
0x40020944 B  REGISTER RGCFR (wo): DMAMUX request generator interrupt clear flag register
0x40020944 C   FIELD 00w01 COF0 (wo): Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
0x40020944 C   FIELD 01w01 COF1 (wo): Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
0x40020944 C   FIELD 02w01 COF2 (wo): Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
0x40020944 C   FIELD 03w01 COF3 (wo): Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.
0x40023000 A PERIPHERAL CRC
0x40023000 B  REGISTER DR (rw): Data register
0x40023000 C   FIELD 00w32 DR: Data register bits
0x40023004 B  REGISTER IDR (rw): Independent data register
0x40023004 C   FIELD 00w32 IDR: General-purpose 32-bit data register bits
0x40023008 B  REGISTER CR: Control register
0x40023008 C   FIELD 00w01 RESET (wo): RESET bit
0x40023008 C   FIELD 03w02 POLYSIZE (rw): Polynomial size These bits control the size of the polynomial.
0x40023008 C   FIELD 05w02 REV_IN (rw): Reverse input data These bits control the reversal of the bit order of the input data
0x40023008 C   FIELD 07w01 REV_OUT (rw): Reverse output data This bit controls the reversal of the bit order of the output data.
0x40023010 B  REGISTER INIT (rw): Initial CRC value
0x40023010 C   FIELD 00w32 CRC_INIT: Programmable initial CRC value
0x40023014 B  REGISTER POL (rw): polynomial
0x40023014 C   FIELD 00w32 POL: Programmable polynomial
0x50000000 A PERIPHERAL GPIOA
0x50000000 B  REGISTER MODER (rw): GPIO port mode register
0x50000000 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50000000 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50000000 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50000000 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50000000 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50000000 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50000000 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50000000 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50000000 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50000000 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50000000 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50000000 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50000000 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50000000 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50000000 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50000000 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50000004 B  REGISTER OTYPER (rw): GPIO port output type register
0x50000004 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50000004 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50000004 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50000004 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50000004 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50000004 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50000004 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50000004 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50000004 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50000004 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50000004 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50000004 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50000004 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50000004 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50000004 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50000004 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50000008 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000008 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50000008 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50000008 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50000008 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50000008 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50000008 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50000008 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50000008 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50000008 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50000008 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50000008 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50000008 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50000008 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50000008 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50000008 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50000008 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000000C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000000C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000000C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000000C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000000C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000000C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000000C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000000C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000000C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000000C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000000C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000000C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000000C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000000C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000000C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000000C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000000C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50000010 B  REGISTER IDR (ro): GPIO port input data register
0x50000010 C   FIELD 00w01 IDR0: Port input data pin 0
0x50000010 C   FIELD 01w01 IDR1: Port input data pin 1
0x50000010 C   FIELD 02w01 IDR2: Port input data pin 2
0x50000010 C   FIELD 03w01 IDR3: Port input data pin 3
0x50000010 C   FIELD 04w01 IDR4: Port input data pin 4
0x50000010 C   FIELD 05w01 IDR5: Port input data pin 5
0x50000010 C   FIELD 06w01 IDR6: Port input data pin 6
0x50000010 C   FIELD 07w01 IDR7: Port input data pin 7
0x50000010 C   FIELD 08w01 IDR8: Port input data pin 8
0x50000010 C   FIELD 09w01 IDR9: Port input data pin 9
0x50000010 C   FIELD 10w01 IDR10: Port input data pin 10
0x50000010 C   FIELD 11w01 IDR11: Port input data pin 11
0x50000010 C   FIELD 12w01 IDR12: Port input data pin 12
0x50000010 C   FIELD 13w01 IDR13: Port input data pin 13
0x50000010 C   FIELD 14w01 IDR14: Port input data pin 14
0x50000010 C   FIELD 15w01 IDR15: Port input data pin 15
0x50000014 B  REGISTER ODR (rw): GPIO port output data register
0x50000014 C   FIELD 00w01 ODR0: Port output data pin 0
0x50000014 C   FIELD 01w01 ODR1: Port output data pin 1
0x50000014 C   FIELD 02w01 ODR2: Port output data pin 2
0x50000014 C   FIELD 03w01 ODR3: Port output data pin 3
0x50000014 C   FIELD 04w01 ODR4: Port output data pin 4
0x50000014 C   FIELD 05w01 ODR5: Port output data pin 5
0x50000014 C   FIELD 06w01 ODR6: Port output data pin 6
0x50000014 C   FIELD 07w01 ODR7: Port output data pin 7
0x50000014 C   FIELD 08w01 ODR8: Port output data pin 8
0x50000014 C   FIELD 09w01 ODR9: Port output data pin 9
0x50000014 C   FIELD 10w01 ODR10: Port output data pin 10
0x50000014 C   FIELD 11w01 ODR11: Port output data pin 11
0x50000014 C   FIELD 12w01 ODR12: Port output data pin 12
0x50000014 C   FIELD 13w01 ODR13: Port output data pin 13
0x50000014 C   FIELD 14w01 ODR14: Port output data pin 14
0x50000014 C   FIELD 15w01 ODR15: Port output data pin 15
0x50000018 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50000018 C   FIELD 00w01 BS0: Port x set pin 0
0x50000018 C   FIELD 01w01 BS1: Port x set pin 1
0x50000018 C   FIELD 02w01 BS2: Port x set pin 2
0x50000018 C   FIELD 03w01 BS3: Port x set pin 3
0x50000018 C   FIELD 04w01 BS4: Port x set pin 4
0x50000018 C   FIELD 05w01 BS5: Port x set pin 5
0x50000018 C   FIELD 06w01 BS6: Port x set pin 6
0x50000018 C   FIELD 07w01 BS7: Port x set pin 7
0x50000018 C   FIELD 08w01 BS8: Port x set pin 8
0x50000018 C   FIELD 09w01 BS9: Port x set pin 9
0x50000018 C   FIELD 10w01 BS10: Port x set pin 10
0x50000018 C   FIELD 11w01 BS11: Port x set pin 11
0x50000018 C   FIELD 12w01 BS12: Port x set pin 12
0x50000018 C   FIELD 13w01 BS13: Port x set pin 13
0x50000018 C   FIELD 14w01 BS14: Port x set pin 14
0x50000018 C   FIELD 15w01 BS15: Port x set pin 15
0x50000018 C   FIELD 16w01 BR0: Port x reset pin 0
0x50000018 C   FIELD 17w01 BR1: Port x reset pin 1
0x50000018 C   FIELD 18w01 BR2: Port x reset pin 2
0x50000018 C   FIELD 19w01 BR3: Port x reset pin 3
0x50000018 C   FIELD 20w01 BR4: Port x reset pin 4
0x50000018 C   FIELD 21w01 BR5: Port x reset pin 5
0x50000018 C   FIELD 22w01 BR6: Port x reset pin 6
0x50000018 C   FIELD 23w01 BR7: Port x reset pin 7
0x50000018 C   FIELD 24w01 BR8: Port x reset pin 8
0x50000018 C   FIELD 25w01 BR9: Port x reset pin 9
0x50000018 C   FIELD 26w01 BR10: Port x reset pin 10
0x50000018 C   FIELD 27w01 BR11: Port x reset pin 11
0x50000018 C   FIELD 28w01 BR12: Port x reset pin 12
0x50000018 C   FIELD 29w01 BR13: Port x reset pin 13
0x50000018 C   FIELD 30w01 BR14: Port x reset pin 14
0x50000018 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000001C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000001C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000001C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000001C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000001C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000001C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000001C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000001C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000001C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000001C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000001C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000001C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000001C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000001C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000001C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000001C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000001C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000001C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50000020 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50000020 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50000024 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50000024 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50000028 B  REGISTER BRR (wo): port bit reset register
0x50000028 C   FIELD 00w01 BR0: Port x reset pin 0
0x50000028 C   FIELD 01w01 BR1: Port x reset pin 1
0x50000028 C   FIELD 02w01 BR2: Port x reset pin 2
0x50000028 C   FIELD 03w01 BR3: Port x reset pin 3
0x50000028 C   FIELD 04w01 BR4: Port x reset pin 4
0x50000028 C   FIELD 05w01 BR5: Port x reset pin 5
0x50000028 C   FIELD 06w01 BR6: Port x reset pin 6
0x50000028 C   FIELD 07w01 BR7: Port x reset pin 7
0x50000028 C   FIELD 08w01 BR8: Port x reset pin 8
0x50000028 C   FIELD 09w01 BR9: Port x reset pin 9
0x50000028 C   FIELD 10w01 BR10: Port x reset pin 10
0x50000028 C   FIELD 11w01 BR11: Port x reset pin 11
0x50000028 C   FIELD 12w01 BR12: Port x reset pin 12
0x50000028 C   FIELD 13w01 BR13: Port x reset pin 13
0x50000028 C   FIELD 14w01 BR14: Port x reset pin 14
0x50000028 C   FIELD 15w01 BR15: Port x reset pin 15
0x50000400 A PERIPHERAL GPIOB
0x50000400 B  REGISTER MODER (rw): GPIO port mode register
0x50000400 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50000400 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50000400 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50000400 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50000400 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50000400 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50000400 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50000400 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50000400 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50000400 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50000400 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50000400 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50000400 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50000400 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50000400 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50000400 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50000404 B  REGISTER OTYPER (rw): GPIO port output type register
0x50000404 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50000404 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50000404 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50000404 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50000404 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50000404 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50000404 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50000404 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50000404 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50000404 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50000404 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50000404 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50000404 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50000404 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50000404 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50000404 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50000408 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000408 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50000408 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50000408 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50000408 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50000408 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50000408 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50000408 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50000408 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50000408 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50000408 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50000408 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50000408 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50000408 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50000408 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50000408 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50000408 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000040C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000040C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000040C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000040C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000040C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000040C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000040C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000040C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000040C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000040C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000040C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000040C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000040C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000040C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000040C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000040C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000040C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50000410 B  REGISTER IDR (ro): GPIO port input data register
0x50000410 C   FIELD 00w01 IDR0: Port input data pin 0
0x50000410 C   FIELD 01w01 IDR1: Port input data pin 1
0x50000410 C   FIELD 02w01 IDR2: Port input data pin 2
0x50000410 C   FIELD 03w01 IDR3: Port input data pin 3
0x50000410 C   FIELD 04w01 IDR4: Port input data pin 4
0x50000410 C   FIELD 05w01 IDR5: Port input data pin 5
0x50000410 C   FIELD 06w01 IDR6: Port input data pin 6
0x50000410 C   FIELD 07w01 IDR7: Port input data pin 7
0x50000410 C   FIELD 08w01 IDR8: Port input data pin 8
0x50000410 C   FIELD 09w01 IDR9: Port input data pin 9
0x50000410 C   FIELD 10w01 IDR10: Port input data pin 10
0x50000410 C   FIELD 11w01 IDR11: Port input data pin 11
0x50000410 C   FIELD 12w01 IDR12: Port input data pin 12
0x50000410 C   FIELD 13w01 IDR13: Port input data pin 13
0x50000410 C   FIELD 14w01 IDR14: Port input data pin 14
0x50000410 C   FIELD 15w01 IDR15: Port input data pin 15
0x50000414 B  REGISTER ODR (rw): GPIO port output data register
0x50000414 C   FIELD 00w01 ODR0: Port output data pin 0
0x50000414 C   FIELD 01w01 ODR1: Port output data pin 1
0x50000414 C   FIELD 02w01 ODR2: Port output data pin 2
0x50000414 C   FIELD 03w01 ODR3: Port output data pin 3
0x50000414 C   FIELD 04w01 ODR4: Port output data pin 4
0x50000414 C   FIELD 05w01 ODR5: Port output data pin 5
0x50000414 C   FIELD 06w01 ODR6: Port output data pin 6
0x50000414 C   FIELD 07w01 ODR7: Port output data pin 7
0x50000414 C   FIELD 08w01 ODR8: Port output data pin 8
0x50000414 C   FIELD 09w01 ODR9: Port output data pin 9
0x50000414 C   FIELD 10w01 ODR10: Port output data pin 10
0x50000414 C   FIELD 11w01 ODR11: Port output data pin 11
0x50000414 C   FIELD 12w01 ODR12: Port output data pin 12
0x50000414 C   FIELD 13w01 ODR13: Port output data pin 13
0x50000414 C   FIELD 14w01 ODR14: Port output data pin 14
0x50000414 C   FIELD 15w01 ODR15: Port output data pin 15
0x50000418 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50000418 C   FIELD 00w01 BS0: Port x set pin 0
0x50000418 C   FIELD 01w01 BS1: Port x set pin 1
0x50000418 C   FIELD 02w01 BS2: Port x set pin 2
0x50000418 C   FIELD 03w01 BS3: Port x set pin 3
0x50000418 C   FIELD 04w01 BS4: Port x set pin 4
0x50000418 C   FIELD 05w01 BS5: Port x set pin 5
0x50000418 C   FIELD 06w01 BS6: Port x set pin 6
0x50000418 C   FIELD 07w01 BS7: Port x set pin 7
0x50000418 C   FIELD 08w01 BS8: Port x set pin 8
0x50000418 C   FIELD 09w01 BS9: Port x set pin 9
0x50000418 C   FIELD 10w01 BS10: Port x set pin 10
0x50000418 C   FIELD 11w01 BS11: Port x set pin 11
0x50000418 C   FIELD 12w01 BS12: Port x set pin 12
0x50000418 C   FIELD 13w01 BS13: Port x set pin 13
0x50000418 C   FIELD 14w01 BS14: Port x set pin 14
0x50000418 C   FIELD 15w01 BS15: Port x set pin 15
0x50000418 C   FIELD 16w01 BR0: Port x reset pin 0
0x50000418 C   FIELD 17w01 BR1: Port x reset pin 1
0x50000418 C   FIELD 18w01 BR2: Port x reset pin 2
0x50000418 C   FIELD 19w01 BR3: Port x reset pin 3
0x50000418 C   FIELD 20w01 BR4: Port x reset pin 4
0x50000418 C   FIELD 21w01 BR5: Port x reset pin 5
0x50000418 C   FIELD 22w01 BR6: Port x reset pin 6
0x50000418 C   FIELD 23w01 BR7: Port x reset pin 7
0x50000418 C   FIELD 24w01 BR8: Port x reset pin 8
0x50000418 C   FIELD 25w01 BR9: Port x reset pin 9
0x50000418 C   FIELD 26w01 BR10: Port x reset pin 10
0x50000418 C   FIELD 27w01 BR11: Port x reset pin 11
0x50000418 C   FIELD 28w01 BR12: Port x reset pin 12
0x50000418 C   FIELD 29w01 BR13: Port x reset pin 13
0x50000418 C   FIELD 30w01 BR14: Port x reset pin 14
0x50000418 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000041C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000041C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000041C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000041C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000041C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000041C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000041C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000041C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000041C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000041C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000041C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000041C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000041C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000041C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000041C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000041C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000041C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000041C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50000420 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50000420 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50000420 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50000424 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50000424 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50000424 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50000428 B  REGISTER BRR (wo): port bit reset register
0x50000428 C   FIELD 00w01 BR0: Port x reset pin 0
0x50000428 C   FIELD 01w01 BR1: Port x reset pin 1
0x50000428 C   FIELD 02w01 BR2: Port x reset pin 2
0x50000428 C   FIELD 03w01 BR3: Port x reset pin 3
0x50000428 C   FIELD 04w01 BR4: Port x reset pin 4
0x50000428 C   FIELD 05w01 BR5: Port x reset pin 5
0x50000428 C   FIELD 06w01 BR6: Port x reset pin 6
0x50000428 C   FIELD 07w01 BR7: Port x reset pin 7
0x50000428 C   FIELD 08w01 BR8: Port x reset pin 8
0x50000428 C   FIELD 09w01 BR9: Port x reset pin 9
0x50000428 C   FIELD 10w01 BR10: Port x reset pin 10
0x50000428 C   FIELD 11w01 BR11: Port x reset pin 11
0x50000428 C   FIELD 12w01 BR12: Port x reset pin 12
0x50000428 C   FIELD 13w01 BR13: Port x reset pin 13
0x50000428 C   FIELD 14w01 BR14: Port x reset pin 14
0x50000428 C   FIELD 15w01 BR15: Port x reset pin 15
0x50000800 A PERIPHERAL GPIOC
0x50000800 B  REGISTER MODER (rw): GPIO port mode register
0x50000800 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50000800 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50000800 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50000800 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50000800 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50000800 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50000800 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50000800 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50000800 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50000800 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50000800 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50000800 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50000800 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50000800 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50000800 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50000800 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50000804 B  REGISTER OTYPER (rw): GPIO port output type register
0x50000804 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50000804 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50000804 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50000804 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50000804 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50000804 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50000804 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50000804 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50000804 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50000804 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50000804 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50000804 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50000804 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50000804 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50000804 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50000804 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50000808 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000808 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50000808 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50000808 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50000808 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50000808 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50000808 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50000808 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50000808 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50000808 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50000808 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50000808 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50000808 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50000808 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50000808 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50000808 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50000808 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000080C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000080C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000080C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000080C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000080C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000080C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000080C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000080C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000080C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000080C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000080C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000080C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000080C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000080C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000080C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000080C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000080C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50000810 B  REGISTER IDR (ro): GPIO port input data register
0x50000810 C   FIELD 00w01 IDR0: Port input data pin 0
0x50000810 C   FIELD 01w01 IDR1: Port input data pin 1
0x50000810 C   FIELD 02w01 IDR2: Port input data pin 2
0x50000810 C   FIELD 03w01 IDR3: Port input data pin 3
0x50000810 C   FIELD 04w01 IDR4: Port input data pin 4
0x50000810 C   FIELD 05w01 IDR5: Port input data pin 5
0x50000810 C   FIELD 06w01 IDR6: Port input data pin 6
0x50000810 C   FIELD 07w01 IDR7: Port input data pin 7
0x50000810 C   FIELD 08w01 IDR8: Port input data pin 8
0x50000810 C   FIELD 09w01 IDR9: Port input data pin 9
0x50000810 C   FIELD 10w01 IDR10: Port input data pin 10
0x50000810 C   FIELD 11w01 IDR11: Port input data pin 11
0x50000810 C   FIELD 12w01 IDR12: Port input data pin 12
0x50000810 C   FIELD 13w01 IDR13: Port input data pin 13
0x50000810 C   FIELD 14w01 IDR14: Port input data pin 14
0x50000810 C   FIELD 15w01 IDR15: Port input data pin 15
0x50000814 B  REGISTER ODR (rw): GPIO port output data register
0x50000814 C   FIELD 00w01 ODR0: Port output data pin 0
0x50000814 C   FIELD 01w01 ODR1: Port output data pin 1
0x50000814 C   FIELD 02w01 ODR2: Port output data pin 2
0x50000814 C   FIELD 03w01 ODR3: Port output data pin 3
0x50000814 C   FIELD 04w01 ODR4: Port output data pin 4
0x50000814 C   FIELD 05w01 ODR5: Port output data pin 5
0x50000814 C   FIELD 06w01 ODR6: Port output data pin 6
0x50000814 C   FIELD 07w01 ODR7: Port output data pin 7
0x50000814 C   FIELD 08w01 ODR8: Port output data pin 8
0x50000814 C   FIELD 09w01 ODR9: Port output data pin 9
0x50000814 C   FIELD 10w01 ODR10: Port output data pin 10
0x50000814 C   FIELD 11w01 ODR11: Port output data pin 11
0x50000814 C   FIELD 12w01 ODR12: Port output data pin 12
0x50000814 C   FIELD 13w01 ODR13: Port output data pin 13
0x50000814 C   FIELD 14w01 ODR14: Port output data pin 14
0x50000814 C   FIELD 15w01 ODR15: Port output data pin 15
0x50000818 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50000818 C   FIELD 00w01 BS0: Port x set pin 0
0x50000818 C   FIELD 01w01 BS1: Port x set pin 1
0x50000818 C   FIELD 02w01 BS2: Port x set pin 2
0x50000818 C   FIELD 03w01 BS3: Port x set pin 3
0x50000818 C   FIELD 04w01 BS4: Port x set pin 4
0x50000818 C   FIELD 05w01 BS5: Port x set pin 5
0x50000818 C   FIELD 06w01 BS6: Port x set pin 6
0x50000818 C   FIELD 07w01 BS7: Port x set pin 7
0x50000818 C   FIELD 08w01 BS8: Port x set pin 8
0x50000818 C   FIELD 09w01 BS9: Port x set pin 9
0x50000818 C   FIELD 10w01 BS10: Port x set pin 10
0x50000818 C   FIELD 11w01 BS11: Port x set pin 11
0x50000818 C   FIELD 12w01 BS12: Port x set pin 12
0x50000818 C   FIELD 13w01 BS13: Port x set pin 13
0x50000818 C   FIELD 14w01 BS14: Port x set pin 14
0x50000818 C   FIELD 15w01 BS15: Port x set pin 15
0x50000818 C   FIELD 16w01 BR0: Port x reset pin 0
0x50000818 C   FIELD 17w01 BR1: Port x reset pin 1
0x50000818 C   FIELD 18w01 BR2: Port x reset pin 2
0x50000818 C   FIELD 19w01 BR3: Port x reset pin 3
0x50000818 C   FIELD 20w01 BR4: Port x reset pin 4
0x50000818 C   FIELD 21w01 BR5: Port x reset pin 5
0x50000818 C   FIELD 22w01 BR6: Port x reset pin 6
0x50000818 C   FIELD 23w01 BR7: Port x reset pin 7
0x50000818 C   FIELD 24w01 BR8: Port x reset pin 8
0x50000818 C   FIELD 25w01 BR9: Port x reset pin 9
0x50000818 C   FIELD 26w01 BR10: Port x reset pin 10
0x50000818 C   FIELD 27w01 BR11: Port x reset pin 11
0x50000818 C   FIELD 28w01 BR12: Port x reset pin 12
0x50000818 C   FIELD 29w01 BR13: Port x reset pin 13
0x50000818 C   FIELD 30w01 BR14: Port x reset pin 14
0x50000818 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000081C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000081C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000081C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000081C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000081C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000081C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000081C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000081C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000081C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000081C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000081C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000081C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000081C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000081C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000081C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000081C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000081C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000081C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50000820 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50000820 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50000820 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50000824 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50000824 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50000824 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50000828 B  REGISTER BRR (wo): port bit reset register
0x50000828 C   FIELD 00w01 BR0: Port x reset pin 0
0x50000828 C   FIELD 01w01 BR1: Port x reset pin 1
0x50000828 C   FIELD 02w01 BR2: Port x reset pin 2
0x50000828 C   FIELD 03w01 BR3: Port x reset pin 3
0x50000828 C   FIELD 04w01 BR4: Port x reset pin 4
0x50000828 C   FIELD 05w01 BR5: Port x reset pin 5
0x50000828 C   FIELD 06w01 BR6: Port x reset pin 6
0x50000828 C   FIELD 07w01 BR7: Port x reset pin 7
0x50000828 C   FIELD 08w01 BR8: Port x reset pin 8
0x50000828 C   FIELD 09w01 BR9: Port x reset pin 9
0x50000828 C   FIELD 10w01 BR10: Port x reset pin 10
0x50000828 C   FIELD 11w01 BR11: Port x reset pin 11
0x50000828 C   FIELD 12w01 BR12: Port x reset pin 12
0x50000828 C   FIELD 13w01 BR13: Port x reset pin 13
0x50000828 C   FIELD 14w01 BR14: Port x reset pin 14
0x50000828 C   FIELD 15w01 BR15: Port x reset pin 15
0x50000C00 A PERIPHERAL GPIOD
0x50000C00 B  REGISTER MODER (rw): GPIO port mode register
0x50000C00 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50000C00 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50000C00 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50000C00 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50000C00 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50000C00 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50000C00 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50000C00 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50000C00 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50000C00 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50000C00 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50000C00 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50000C00 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50000C00 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50000C00 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50000C00 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50000C04 B  REGISTER OTYPER (rw): GPIO port output type register
0x50000C04 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50000C04 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50000C04 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50000C04 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50000C04 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50000C04 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50000C04 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50000C04 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50000C04 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50000C04 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50000C04 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50000C04 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50000C04 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50000C04 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50000C04 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50000C04 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50000C08 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000C08 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50000C08 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50000C08 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50000C08 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50000C08 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50000C08 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50000C08 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50000C08 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50000C08 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50000C08 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50000C08 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50000C08 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50000C08 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50000C08 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50000C08 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50000C08 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x50000C0C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x50000C0C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x50000C0C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x50000C0C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x50000C0C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x50000C0C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x50000C0C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x50000C0C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x50000C0C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x50000C0C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x50000C0C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x50000C0C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x50000C0C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x50000C0C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x50000C0C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x50000C0C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x50000C0C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50000C10 B  REGISTER IDR (ro): GPIO port input data register
0x50000C10 C   FIELD 00w01 IDR0: Port input data pin 0
0x50000C10 C   FIELD 01w01 IDR1: Port input data pin 1
0x50000C10 C   FIELD 02w01 IDR2: Port input data pin 2
0x50000C10 C   FIELD 03w01 IDR3: Port input data pin 3
0x50000C10 C   FIELD 04w01 IDR4: Port input data pin 4
0x50000C10 C   FIELD 05w01 IDR5: Port input data pin 5
0x50000C10 C   FIELD 06w01 IDR6: Port input data pin 6
0x50000C10 C   FIELD 07w01 IDR7: Port input data pin 7
0x50000C10 C   FIELD 08w01 IDR8: Port input data pin 8
0x50000C10 C   FIELD 09w01 IDR9: Port input data pin 9
0x50000C10 C   FIELD 10w01 IDR10: Port input data pin 10
0x50000C10 C   FIELD 11w01 IDR11: Port input data pin 11
0x50000C10 C   FIELD 12w01 IDR12: Port input data pin 12
0x50000C10 C   FIELD 13w01 IDR13: Port input data pin 13
0x50000C10 C   FIELD 14w01 IDR14: Port input data pin 14
0x50000C10 C   FIELD 15w01 IDR15: Port input data pin 15
0x50000C14 B  REGISTER ODR (rw): GPIO port output data register
0x50000C14 C   FIELD 00w01 ODR0: Port output data pin 0
0x50000C14 C   FIELD 01w01 ODR1: Port output data pin 1
0x50000C14 C   FIELD 02w01 ODR2: Port output data pin 2
0x50000C14 C   FIELD 03w01 ODR3: Port output data pin 3
0x50000C14 C   FIELD 04w01 ODR4: Port output data pin 4
0x50000C14 C   FIELD 05w01 ODR5: Port output data pin 5
0x50000C14 C   FIELD 06w01 ODR6: Port output data pin 6
0x50000C14 C   FIELD 07w01 ODR7: Port output data pin 7
0x50000C14 C   FIELD 08w01 ODR8: Port output data pin 8
0x50000C14 C   FIELD 09w01 ODR9: Port output data pin 9
0x50000C14 C   FIELD 10w01 ODR10: Port output data pin 10
0x50000C14 C   FIELD 11w01 ODR11: Port output data pin 11
0x50000C14 C   FIELD 12w01 ODR12: Port output data pin 12
0x50000C14 C   FIELD 13w01 ODR13: Port output data pin 13
0x50000C14 C   FIELD 14w01 ODR14: Port output data pin 14
0x50000C14 C   FIELD 15w01 ODR15: Port output data pin 15
0x50000C18 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50000C18 C   FIELD 00w01 BS0: Port x set pin 0
0x50000C18 C   FIELD 01w01 BS1: Port x set pin 1
0x50000C18 C   FIELD 02w01 BS2: Port x set pin 2
0x50000C18 C   FIELD 03w01 BS3: Port x set pin 3
0x50000C18 C   FIELD 04w01 BS4: Port x set pin 4
0x50000C18 C   FIELD 05w01 BS5: Port x set pin 5
0x50000C18 C   FIELD 06w01 BS6: Port x set pin 6
0x50000C18 C   FIELD 07w01 BS7: Port x set pin 7
0x50000C18 C   FIELD 08w01 BS8: Port x set pin 8
0x50000C18 C   FIELD 09w01 BS9: Port x set pin 9
0x50000C18 C   FIELD 10w01 BS10: Port x set pin 10
0x50000C18 C   FIELD 11w01 BS11: Port x set pin 11
0x50000C18 C   FIELD 12w01 BS12: Port x set pin 12
0x50000C18 C   FIELD 13w01 BS13: Port x set pin 13
0x50000C18 C   FIELD 14w01 BS14: Port x set pin 14
0x50000C18 C   FIELD 15w01 BS15: Port x set pin 15
0x50000C18 C   FIELD 16w01 BR0: Port x reset pin 0
0x50000C18 C   FIELD 17w01 BR1: Port x reset pin 1
0x50000C18 C   FIELD 18w01 BR2: Port x reset pin 2
0x50000C18 C   FIELD 19w01 BR3: Port x reset pin 3
0x50000C18 C   FIELD 20w01 BR4: Port x reset pin 4
0x50000C18 C   FIELD 21w01 BR5: Port x reset pin 5
0x50000C18 C   FIELD 22w01 BR6: Port x reset pin 6
0x50000C18 C   FIELD 23w01 BR7: Port x reset pin 7
0x50000C18 C   FIELD 24w01 BR8: Port x reset pin 8
0x50000C18 C   FIELD 25w01 BR9: Port x reset pin 9
0x50000C18 C   FIELD 26w01 BR10: Port x reset pin 10
0x50000C18 C   FIELD 27w01 BR11: Port x reset pin 11
0x50000C18 C   FIELD 28w01 BR12: Port x reset pin 12
0x50000C18 C   FIELD 29w01 BR13: Port x reset pin 13
0x50000C18 C   FIELD 30w01 BR14: Port x reset pin 14
0x50000C18 C   FIELD 31w01 BR15: Port x reset pin 15
0x50000C1C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x50000C1C C   FIELD 00w01 LCK0: Port x lock pin 0
0x50000C1C C   FIELD 01w01 LCK1: Port x lock pin 1
0x50000C1C C   FIELD 02w01 LCK2: Port x lock pin 2
0x50000C1C C   FIELD 03w01 LCK3: Port x lock pin 3
0x50000C1C C   FIELD 04w01 LCK4: Port x lock pin 4
0x50000C1C C   FIELD 05w01 LCK5: Port x lock pin 5
0x50000C1C C   FIELD 06w01 LCK6: Port x lock pin 6
0x50000C1C C   FIELD 07w01 LCK7: Port x lock pin 7
0x50000C1C C   FIELD 08w01 LCK8: Port x lock pin 8
0x50000C1C C   FIELD 09w01 LCK9: Port x lock pin 9
0x50000C1C C   FIELD 10w01 LCK10: Port x lock pin 10
0x50000C1C C   FIELD 11w01 LCK11: Port x lock pin 11
0x50000C1C C   FIELD 12w01 LCK12: Port x lock pin 12
0x50000C1C C   FIELD 13w01 LCK13: Port x lock pin 13
0x50000C1C C   FIELD 14w01 LCK14: Port x lock pin 14
0x50000C1C C   FIELD 15w01 LCK15: Port x lock pin 15
0x50000C1C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50000C20 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50000C20 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50000C20 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50000C24 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50000C24 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50000C24 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50000C28 B  REGISTER BRR (wo): port bit reset register
0x50000C28 C   FIELD 00w01 BR0: Port x reset pin 0
0x50000C28 C   FIELD 01w01 BR1: Port x reset pin 1
0x50000C28 C   FIELD 02w01 BR2: Port x reset pin 2
0x50000C28 C   FIELD 03w01 BR3: Port x reset pin 3
0x50000C28 C   FIELD 04w01 BR4: Port x reset pin 4
0x50000C28 C   FIELD 05w01 BR5: Port x reset pin 5
0x50000C28 C   FIELD 06w01 BR6: Port x reset pin 6
0x50000C28 C   FIELD 07w01 BR7: Port x reset pin 7
0x50000C28 C   FIELD 08w01 BR8: Port x reset pin 8
0x50000C28 C   FIELD 09w01 BR9: Port x reset pin 9
0x50000C28 C   FIELD 10w01 BR10: Port x reset pin 10
0x50000C28 C   FIELD 11w01 BR11: Port x reset pin 11
0x50000C28 C   FIELD 12w01 BR12: Port x reset pin 12
0x50000C28 C   FIELD 13w01 BR13: Port x reset pin 13
0x50000C28 C   FIELD 14w01 BR14: Port x reset pin 14
0x50000C28 C   FIELD 15w01 BR15: Port x reset pin 15
0x50001000 A PERIPHERAL GPIOE
0x50001000 B  REGISTER MODER (rw): GPIO port mode register
0x50001000 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50001000 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50001000 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50001000 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50001000 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50001000 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50001000 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50001000 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50001000 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50001000 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50001000 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50001000 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50001000 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50001000 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50001000 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50001000 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50001004 B  REGISTER OTYPER (rw): GPIO port output type register
0x50001004 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50001004 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50001004 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50001004 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50001004 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50001004 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50001004 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50001004 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50001004 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50001004 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50001004 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50001004 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50001004 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50001004 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50001004 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50001004 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50001008 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50001008 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50001008 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50001008 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50001008 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50001008 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50001008 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50001008 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50001008 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50001008 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50001008 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50001008 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50001008 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50001008 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50001008 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50001008 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50001008 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000100C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000100C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000100C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000100C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000100C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000100C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000100C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000100C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000100C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000100C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000100C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000100C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000100C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000100C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000100C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000100C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000100C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50001010 B  REGISTER IDR (ro): GPIO port input data register
0x50001010 C   FIELD 00w01 IDR0: Port input data pin 0
0x50001010 C   FIELD 01w01 IDR1: Port input data pin 1
0x50001010 C   FIELD 02w01 IDR2: Port input data pin 2
0x50001010 C   FIELD 03w01 IDR3: Port input data pin 3
0x50001010 C   FIELD 04w01 IDR4: Port input data pin 4
0x50001010 C   FIELD 05w01 IDR5: Port input data pin 5
0x50001010 C   FIELD 06w01 IDR6: Port input data pin 6
0x50001010 C   FIELD 07w01 IDR7: Port input data pin 7
0x50001010 C   FIELD 08w01 IDR8: Port input data pin 8
0x50001010 C   FIELD 09w01 IDR9: Port input data pin 9
0x50001010 C   FIELD 10w01 IDR10: Port input data pin 10
0x50001010 C   FIELD 11w01 IDR11: Port input data pin 11
0x50001010 C   FIELD 12w01 IDR12: Port input data pin 12
0x50001010 C   FIELD 13w01 IDR13: Port input data pin 13
0x50001010 C   FIELD 14w01 IDR14: Port input data pin 14
0x50001010 C   FIELD 15w01 IDR15: Port input data pin 15
0x50001014 B  REGISTER ODR (rw): GPIO port output data register
0x50001014 C   FIELD 00w01 ODR0: Port output data pin 0
0x50001014 C   FIELD 01w01 ODR1: Port output data pin 1
0x50001014 C   FIELD 02w01 ODR2: Port output data pin 2
0x50001014 C   FIELD 03w01 ODR3: Port output data pin 3
0x50001014 C   FIELD 04w01 ODR4: Port output data pin 4
0x50001014 C   FIELD 05w01 ODR5: Port output data pin 5
0x50001014 C   FIELD 06w01 ODR6: Port output data pin 6
0x50001014 C   FIELD 07w01 ODR7: Port output data pin 7
0x50001014 C   FIELD 08w01 ODR8: Port output data pin 8
0x50001014 C   FIELD 09w01 ODR9: Port output data pin 9
0x50001014 C   FIELD 10w01 ODR10: Port output data pin 10
0x50001014 C   FIELD 11w01 ODR11: Port output data pin 11
0x50001014 C   FIELD 12w01 ODR12: Port output data pin 12
0x50001014 C   FIELD 13w01 ODR13: Port output data pin 13
0x50001014 C   FIELD 14w01 ODR14: Port output data pin 14
0x50001014 C   FIELD 15w01 ODR15: Port output data pin 15
0x50001018 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50001018 C   FIELD 00w01 BS0: Port x set pin 0
0x50001018 C   FIELD 01w01 BS1: Port x set pin 1
0x50001018 C   FIELD 02w01 BS2: Port x set pin 2
0x50001018 C   FIELD 03w01 BS3: Port x set pin 3
0x50001018 C   FIELD 04w01 BS4: Port x set pin 4
0x50001018 C   FIELD 05w01 BS5: Port x set pin 5
0x50001018 C   FIELD 06w01 BS6: Port x set pin 6
0x50001018 C   FIELD 07w01 BS7: Port x set pin 7
0x50001018 C   FIELD 08w01 BS8: Port x set pin 8
0x50001018 C   FIELD 09w01 BS9: Port x set pin 9
0x50001018 C   FIELD 10w01 BS10: Port x set pin 10
0x50001018 C   FIELD 11w01 BS11: Port x set pin 11
0x50001018 C   FIELD 12w01 BS12: Port x set pin 12
0x50001018 C   FIELD 13w01 BS13: Port x set pin 13
0x50001018 C   FIELD 14w01 BS14: Port x set pin 14
0x50001018 C   FIELD 15w01 BS15: Port x set pin 15
0x50001018 C   FIELD 16w01 BR0: Port x reset pin 0
0x50001018 C   FIELD 17w01 BR1: Port x reset pin 1
0x50001018 C   FIELD 18w01 BR2: Port x reset pin 2
0x50001018 C   FIELD 19w01 BR3: Port x reset pin 3
0x50001018 C   FIELD 20w01 BR4: Port x reset pin 4
0x50001018 C   FIELD 21w01 BR5: Port x reset pin 5
0x50001018 C   FIELD 22w01 BR6: Port x reset pin 6
0x50001018 C   FIELD 23w01 BR7: Port x reset pin 7
0x50001018 C   FIELD 24w01 BR8: Port x reset pin 8
0x50001018 C   FIELD 25w01 BR9: Port x reset pin 9
0x50001018 C   FIELD 26w01 BR10: Port x reset pin 10
0x50001018 C   FIELD 27w01 BR11: Port x reset pin 11
0x50001018 C   FIELD 28w01 BR12: Port x reset pin 12
0x50001018 C   FIELD 29w01 BR13: Port x reset pin 13
0x50001018 C   FIELD 30w01 BR14: Port x reset pin 14
0x50001018 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000101C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000101C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000101C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000101C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000101C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000101C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000101C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000101C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000101C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000101C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000101C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000101C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000101C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000101C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000101C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000101C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000101C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000101C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50001020 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50001020 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50001020 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50001024 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50001024 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50001024 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50001028 B  REGISTER BRR (wo): port bit reset register
0x50001028 C   FIELD 00w01 BR0: Port x reset pin 0
0x50001028 C   FIELD 01w01 BR1: Port x reset pin 1
0x50001028 C   FIELD 02w01 BR2: Port x reset pin 2
0x50001028 C   FIELD 03w01 BR3: Port x reset pin 3
0x50001028 C   FIELD 04w01 BR4: Port x reset pin 4
0x50001028 C   FIELD 05w01 BR5: Port x reset pin 5
0x50001028 C   FIELD 06w01 BR6: Port x reset pin 6
0x50001028 C   FIELD 07w01 BR7: Port x reset pin 7
0x50001028 C   FIELD 08w01 BR8: Port x reset pin 8
0x50001028 C   FIELD 09w01 BR9: Port x reset pin 9
0x50001028 C   FIELD 10w01 BR10: Port x reset pin 10
0x50001028 C   FIELD 11w01 BR11: Port x reset pin 11
0x50001028 C   FIELD 12w01 BR12: Port x reset pin 12
0x50001028 C   FIELD 13w01 BR13: Port x reset pin 13
0x50001028 C   FIELD 14w01 BR14: Port x reset pin 14
0x50001028 C   FIELD 15w01 BR15: Port x reset pin 15
0x50001400 A PERIPHERAL GPIOF
0x50001400 B  REGISTER MODER (rw): GPIO port mode register
0x50001400 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50001400 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50001400 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50001400 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50001400 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50001400 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50001400 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50001400 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50001400 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50001400 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50001400 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50001400 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50001400 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50001400 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50001400 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50001400 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50001404 B  REGISTER OTYPER (rw): GPIO port output type register
0x50001404 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50001404 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50001404 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50001404 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50001404 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50001404 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50001404 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50001404 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50001404 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50001404 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50001404 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50001404 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50001404 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50001404 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50001404 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50001404 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50001408 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50001408 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50001408 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50001408 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50001408 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50001408 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50001408 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50001408 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50001408 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50001408 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50001408 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50001408 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50001408 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50001408 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50001408 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50001408 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50001408 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000140C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000140C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000140C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000140C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000140C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000140C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000140C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000140C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000140C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000140C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000140C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000140C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000140C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000140C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000140C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000140C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000140C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50001410 B  REGISTER IDR (ro): GPIO port input data register
0x50001410 C   FIELD 00w01 IDR0: Port input data pin 0
0x50001410 C   FIELD 01w01 IDR1: Port input data pin 1
0x50001410 C   FIELD 02w01 IDR2: Port input data pin 2
0x50001410 C   FIELD 03w01 IDR3: Port input data pin 3
0x50001410 C   FIELD 04w01 IDR4: Port input data pin 4
0x50001410 C   FIELD 05w01 IDR5: Port input data pin 5
0x50001410 C   FIELD 06w01 IDR6: Port input data pin 6
0x50001410 C   FIELD 07w01 IDR7: Port input data pin 7
0x50001410 C   FIELD 08w01 IDR8: Port input data pin 8
0x50001410 C   FIELD 09w01 IDR9: Port input data pin 9
0x50001410 C   FIELD 10w01 IDR10: Port input data pin 10
0x50001410 C   FIELD 11w01 IDR11: Port input data pin 11
0x50001410 C   FIELD 12w01 IDR12: Port input data pin 12
0x50001410 C   FIELD 13w01 IDR13: Port input data pin 13
0x50001410 C   FIELD 14w01 IDR14: Port input data pin 14
0x50001410 C   FIELD 15w01 IDR15: Port input data pin 15
0x50001414 B  REGISTER ODR (rw): GPIO port output data register
0x50001414 C   FIELD 00w01 ODR0: Port output data pin 0
0x50001414 C   FIELD 01w01 ODR1: Port output data pin 1
0x50001414 C   FIELD 02w01 ODR2: Port output data pin 2
0x50001414 C   FIELD 03w01 ODR3: Port output data pin 3
0x50001414 C   FIELD 04w01 ODR4: Port output data pin 4
0x50001414 C   FIELD 05w01 ODR5: Port output data pin 5
0x50001414 C   FIELD 06w01 ODR6: Port output data pin 6
0x50001414 C   FIELD 07w01 ODR7: Port output data pin 7
0x50001414 C   FIELD 08w01 ODR8: Port output data pin 8
0x50001414 C   FIELD 09w01 ODR9: Port output data pin 9
0x50001414 C   FIELD 10w01 ODR10: Port output data pin 10
0x50001414 C   FIELD 11w01 ODR11: Port output data pin 11
0x50001414 C   FIELD 12w01 ODR12: Port output data pin 12
0x50001414 C   FIELD 13w01 ODR13: Port output data pin 13
0x50001414 C   FIELD 14w01 ODR14: Port output data pin 14
0x50001414 C   FIELD 15w01 ODR15: Port output data pin 15
0x50001418 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50001418 C   FIELD 00w01 BS0: Port x set pin 0
0x50001418 C   FIELD 01w01 BS1: Port x set pin 1
0x50001418 C   FIELD 02w01 BS2: Port x set pin 2
0x50001418 C   FIELD 03w01 BS3: Port x set pin 3
0x50001418 C   FIELD 04w01 BS4: Port x set pin 4
0x50001418 C   FIELD 05w01 BS5: Port x set pin 5
0x50001418 C   FIELD 06w01 BS6: Port x set pin 6
0x50001418 C   FIELD 07w01 BS7: Port x set pin 7
0x50001418 C   FIELD 08w01 BS8: Port x set pin 8
0x50001418 C   FIELD 09w01 BS9: Port x set pin 9
0x50001418 C   FIELD 10w01 BS10: Port x set pin 10
0x50001418 C   FIELD 11w01 BS11: Port x set pin 11
0x50001418 C   FIELD 12w01 BS12: Port x set pin 12
0x50001418 C   FIELD 13w01 BS13: Port x set pin 13
0x50001418 C   FIELD 14w01 BS14: Port x set pin 14
0x50001418 C   FIELD 15w01 BS15: Port x set pin 15
0x50001418 C   FIELD 16w01 BR0: Port x reset pin 0
0x50001418 C   FIELD 17w01 BR1: Port x reset pin 1
0x50001418 C   FIELD 18w01 BR2: Port x reset pin 2
0x50001418 C   FIELD 19w01 BR3: Port x reset pin 3
0x50001418 C   FIELD 20w01 BR4: Port x reset pin 4
0x50001418 C   FIELD 21w01 BR5: Port x reset pin 5
0x50001418 C   FIELD 22w01 BR6: Port x reset pin 6
0x50001418 C   FIELD 23w01 BR7: Port x reset pin 7
0x50001418 C   FIELD 24w01 BR8: Port x reset pin 8
0x50001418 C   FIELD 25w01 BR9: Port x reset pin 9
0x50001418 C   FIELD 26w01 BR10: Port x reset pin 10
0x50001418 C   FIELD 27w01 BR11: Port x reset pin 11
0x50001418 C   FIELD 28w01 BR12: Port x reset pin 12
0x50001418 C   FIELD 29w01 BR13: Port x reset pin 13
0x50001418 C   FIELD 30w01 BR14: Port x reset pin 14
0x50001418 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000141C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000141C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000141C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000141C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000141C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000141C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000141C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000141C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000141C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000141C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000141C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000141C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000141C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000141C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000141C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000141C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000141C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000141C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50001420 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50001420 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50001420 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50001424 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50001424 C   FIELD 00w04 AFREL8: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 04w04 AFREL9: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 08w04 AFREL10: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 12w04 AFREL11: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 16w04 AFREL12: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 20w04 AFREL13: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 24w04 AFREL14: Alternate function selection for port x bit y (y = 8..15)
0x50001424 C   FIELD 28w04 AFREL15: Alternate function selection for port x bit y (y = 8..15)
0x50001428 B  REGISTER BRR (wo): port bit reset register
0x50001428 C   FIELD 00w01 BR0: Port x reset pin 0
0x50001428 C   FIELD 01w01 BR1: Port x reset pin 1
0x50001428 C   FIELD 02w01 BR2: Port x reset pin 2
0x50001428 C   FIELD 03w01 BR3: Port x reset pin 3
0x50001428 C   FIELD 04w01 BR4: Port x reset pin 4
0x50001428 C   FIELD 05w01 BR5: Port x reset pin 5
0x50001428 C   FIELD 06w01 BR6: Port x reset pin 6
0x50001428 C   FIELD 07w01 BR7: Port x reset pin 7
0x50001428 C   FIELD 08w01 BR8: Port x reset pin 8
0x50001428 C   FIELD 09w01 BR9: Port x reset pin 9
0x50001428 C   FIELD 10w01 BR10: Port x reset pin 10
0x50001428 C   FIELD 11w01 BR11: Port x reset pin 11
0x50001428 C   FIELD 12w01 BR12: Port x reset pin 12
0x50001428 C   FIELD 13w01 BR13: Port x reset pin 13
0x50001428 C   FIELD 14w01 BR14: Port x reset pin 14
0x50001428 C   FIELD 15w01 BR15: Port x reset pin 15
INTERRUPT 000: WWDG (WWDG): Window watchdog interrupt
INTERRUPT 011: DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5 (DMAMUX): DMA1 channel 4, 5, 6, 7, DMAMUX,DMA2 channel 1, 2, 3, 4, 5 interrupts
INTERRUPT 012: ADC (ADC): ADC interrupt (ADC combined with EXTI 17 and 18)
INTERRUPT 013: TIM1_BRK_UP_TRG_COM (TIM1): TIM1 break, update, trigger and commutation interrupts
INTERRUPT 014: TIM1_CC (TIM1): TIM1 Capture Compare interrupt
INTERRUPT 016: TIM3 (TIM3): TIM3 global interrupt
INTERRUPT 017: TIM6 (TIM6): TIM6 global interrupt
INTERRUPT 018: TIM7 (TIM7): TIM7 global interrupt
INTERRUPT 019: TIM14 (TIM14): TIM14 global interrupt
INTERRUPT 020: TIM15 (TIM15): TIM 15 global interrupt
INTERRUPT 021: TIM16 (TIM16): TIM16 global interrupt
INTERRUPT 022: TIM17 (TIM17): TIM17 global interrupt
INTERRUPT 023: I2C1 (I2C1): I2C1 global interrupt
INTERRUPT 024: I2C2 (I2C2): I2C2 global interrupt
INTERRUPT 027: USART1 (USART1): USART1 global interrupt
INTERRUPT 028: USART2 (USART2): USART2 global interrupt