/
gen-insn.c
1402 lines (1296 loc) · 32.9 KB
/
gen-insn.c
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#include "ebpf_fuzzer.h"
static int invalid_reg_used = 0;
static int extra0_reg_used = 0;
static __maybe_unused struct reg_usage regs[MAX_BPF_REG]; /* TODO */
enum jmp_ops {
JMP_OPS_MIN,
JMP_OPS_JNE,
JMP_OPS_JLT,
JMP_OPS_JLE,
JMP_OPS_JSGT,
JMP_OPS_JSGE,
JMP_OPS_JSLT,
JMP_OPS_JSLE,
JMP_OPS_JA,
JMP_OPS_JEQ,
JMP_OPS_JGT,
JMP_OPS_JGE,
JMP_OPS_JSET,
JMP_OPS_MAX,
};
int jmp_ops_codes[] = {
[JMP_OPS_JNE] = BPF_JNE,
[JMP_OPS_JLT] = BPF_JLT,
[JMP_OPS_JLE] = BPF_JLE,
[JMP_OPS_JSGT] = BPF_JSGT,
[JMP_OPS_JSGE] = BPF_JSGE,
[JMP_OPS_JSLT] = BPF_JSLT,
[JMP_OPS_JSLE] = BPF_JSLE,
[JMP_OPS_JA] = BPF_JA,
[JMP_OPS_JEQ] = BPF_JEQ,
[JMP_OPS_JGT] = BPF_JGT,
[JMP_OPS_JGE] = BPF_JGE,
[JMP_OPS_JSET] = BPF_JSET,
};
enum alu_ops {
ALU_OPS_MIN,
ALU_OPS_ADD,
ALU_OPS_SUB,
ALU_OPS_MUL,
ALU_OPS_DIV,
ALU_OPS_OR,
ALU_OPS_AND,
ALU_OPS_LSH,
ALU_OPS_RSH,
ALU_OPS_NEG,
ALU_OPS_MOD,
ALU_OPS_XOR,
ALU_OPS_MAX,
};
int alu_ops_codes[] = {
[ALU_OPS_ADD] = BPF_ADD,
[ALU_OPS_SUB] = BPF_SUB,
[ALU_OPS_MUL] = BPF_MUL,
[ALU_OPS_DIV] = BPF_DIV,
[ALU_OPS_OR] = BPF_OR,
[ALU_OPS_AND] = BPF_AND,
[ALU_OPS_LSH] = BPF_LSH,
[ALU_OPS_RSH] = BPF_RSH,
[ALU_OPS_NEG] = BPF_NEG,
[ALU_OPS_MOD] = BPF_MOD,
[ALU_OPS_XOR] = BPF_XOR,
};
enum insn_generator_idx {
INSN_GENERATOR_MIN,
INSN_GENERATOR_JMP,
INSN_GENERATOR_ALU,
INSN_GENERATOR_MOV,
INSN_GENERATOR_LD,
INSN_GENERATOR_NON,
INSN_GENERATOR_MAX,
};
static inline int rand_ops(int *arr, int min, int max)
{
int idx = rand_range(min, max);
return arr[idx];
}
static inline int rand_jmp_ops(void)
{
return rand_ops(jmp_ops_codes, JMP_OPS_MIN+1, JMP_OPS_MAX);
}
static inline int rand_alu_ops(void)
{
return rand_ops(alu_ops_codes, ALU_OPS_MIN+1, ALU_OPS_MAX);
}
typedef int (*insn_generator)(struct bpf_insn *insns, int *idx);
static int gen_jmp_insn(struct bpf_insn *insns, int *idx);
static int gen_alu_insn(struct bpf_insn *insns, int *idx);
static int gen_mov_insn(struct bpf_insn *insns, int *idx);
static int gen_ld_insn(struct bpf_insn *insns, int *idx);
static int gen_last_insn(struct bpf_insn *insns, int *idx);
static insn_generator generators[] = {
[INSN_GENERATOR_JMP] = gen_jmp_insn,
[INSN_GENERATOR_ALU] = gen_alu_insn,
[INSN_GENERATOR_MOV] = gen_mov_insn,
[INSN_GENERATOR_LD] = gen_ld_insn,
[INSN_GENERATOR_NON] = gen_non_insn,
[INSN_GENERATOR_MAX] = gen_last_insn,
};
static int gen_body0_min_bound(struct bpf_insn *insns, int *idx, long minv,
int _signed, int _64bit)
{
int __idx = *idx;
int reg = SPECIAL_REG;
COPY_INSNS(insns, __idx, BPF_MOV64_IMM(BPF_REG_0, 0));
if (_64bit) {
if (_signed)
COPY_INSNS(insns, __idx, BPF_JMP_IMM(BPF_JSGT, reg, minv, 1));
else
COPY_INSNS(insns, __idx, BPF_JMP_IMM(BPF_JGT, reg, minv, 1));
} else {
if (_signed)
COPY_INSNS(insns, __idx, BPF_JMP32_IMM(BPF_JSGT, reg, minv, 1));
else
COPY_INSNS(insns, __idx, BPF_JMP32_IMM(BPF_JGT, reg, minv, 1));
}
COPY_INSNS(insns, __idx, BPF_EXIT_INSN());
*idx = __idx;
return 0;
}
static int gen_body0_max_bound(struct bpf_insn *insns, int *idx, long maxv,
int _signed, int _64bit)
{
int __idx = *idx;
int reg = SPECIAL_REG;
COPY_INSNS(insns, __idx, BPF_MOV64_IMM(BPF_REG_0, 0));
if (s_rand32() % 2)
COPY_INSNS(insns, __idx, BPF_MOV64_IMM(UMAX_REG, maxv));
else
COPY_INSNS(insns, __idx, BPF_MOV32_IMM(UMAX_REG, maxv));
if (_64bit) {
if (_signed)
COPY_INSNS(insns, __idx, BPF_JMP_REG(BPF_JSLT, reg, UMAX_REG, 1));
else
COPY_INSNS(insns, __idx, BPF_JMP_REG(BPF_JLT, reg, UMAX_REG, 1));
} else {
if (_signed)
COPY_INSNS(insns, __idx, BPF_JMP32_REG(BPF_JSLT, reg, UMAX_REG, 1));
else
COPY_INSNS(insns, __idx, BPF_JMP32_REG(BPF_JLT, reg, UMAX_REG, 1));
}
COPY_INSNS(insns, __idx, BPF_EXIT_INSN());
*idx = __idx;
return 0;
}
static long gen_min_val(void)
{
long v;
v = rand_range(-FUZZ_MAP_SIZE, FUZZ_MAP_SIZE+1);
return v;
}
static long gen_max_val(void)
{
long v;
static unsigned range = 0x100;
static unsigned max_bits = 64;
int bits = rand_range(0, max_bits);
int range_v = rand_range(-range, range+1);
v = (1ULL<<bits);
v += range_v;
return v;
}
static int gen_body0(struct bpf_insn *insns, int *cnt, unsigned long special_v)
{
int err = 0;
int idx = 0;
unsigned long umin = gen_min_val();
unsigned long umax = gen_max_val();
int _signed_max = s_rand32() % 2;
int _64bit_max = s_rand32() % 2;
int _signed_min = s_rand32() % 2;
int _64bit_min = s_rand32() % 2;
COPY_INSNS(insns, idx, BPF_LDX_MEM(BPF_DW, SPECIAL_REG, STORAGE_REG, 0));
if (s_rand32() % 2) {
err = gen_body0_max_bound(insns, &idx, umax, _signed_max,
_64bit_max);
if (err < 0) {
return -1;
}
}
if (s_rand32() % 2) {
err = gen_body0_min_bound(insns, &idx, umin, _signed_min,
_64bit_min);
if (err < 0) {
return -1;
}
}
*cnt = idx;
return 0;
}
static int gen_jmp_insn(struct bpf_insn *insns, int *idx)
{
int __idx = *idx;
int err = 0;
int _64bit = s_rand32() % 2;
int is_imm = s_rand32() % 2;
int op_code = rand_jmp_ops();
if (is_imm) {
long imm_v;
if (_64bit)
imm_v = s_rand64();
else
imm_v = s_rand32();
int reg;
int reg_id = 0;
if (extra0_reg_used) {
reg_id = s_rand32() % 2;
}
if (!reg_id) {
if (invalid_reg_used)
if (s_rand32() % 2)
reg = INVALID_P_REG;
else
reg = SPECIAL_REG;
else
reg = SPECIAL_REG;
} else {
reg = EXTRA0_REG;
}
err = gen_jmp_insn_common(insns, &__idx, is_imm, _64bit, reg,
0, imm_v, op_code);
if (err < 0) {
return -1;
}
} else {
/*
* XXX: pick up two registers in EXTRA0_REG, SPECIAL_REG.
* if INVALID_P_REG is in use, take it instead of SPECIAL_REG.
*/
int reg0, reg1;
if (invalid_reg_used) {
if (s_rand32() % 2)
reg0 = INVALID_P_REG;
else
reg0 = SPECIAL_REG;
} else {
reg0 = SPECIAL_REG;
}
if (!extra0_reg_used) {
/* XXX: set the EXTRA0_REG first */
if (s_rand32() % 2) {
err = gen_ld_insn_common(insns, &__idx,
EXTRA0_REG,
s_rand64());
} else {
err = gen_mov_insn_common(insns, &__idx, 1,
s_rand32() % 2,
EXTRA0_REG, 0,
s_rand64());
}
if (err < 0) {
return -1;
}
extra0_reg_used = 1;
}
if (s_rand32() % 2) {
reg1 = reg0;
reg0 = EXTRA0_REG;
} else {
reg1 = EXTRA0_REG;
}
err = gen_jmp_insn_common(insns, &__idx, is_imm, _64bit,
reg0, reg1, 0, op_code);
if (err < 0) {
return -1;
}
}
*idx = __idx;
return 0;
}
static int gen_alu_insn(struct bpf_insn *insns, int *idx)
{
int __idx = *idx;
int err = 0;
int _64bit = s_rand32() % 2;
int is_imm = s_rand32() % 2;
int op_code = rand_alu_ops();
if (is_imm) {
long imm_v;
if (_64bit)
imm_v = s_rand64();
else
imm_v = s_rand32();
int reg;
int reg_id = 0;
if (extra0_reg_used) {
reg_id = s_rand32() % 2;
}
if (!reg_id) {
if (invalid_reg_used)
if (s_rand32() % 2)
reg = INVALID_P_REG;
else
reg = SPECIAL_REG;
else
reg = SPECIAL_REG;
} else {
reg = EXTRA0_REG;
}
err = gen_alu_insn_common(insns, &__idx, is_imm, _64bit, reg,
0, imm_v, op_code);
if (err < 0) {
return -1;
}
} else {
int reg0, reg1;
if (invalid_reg_used) {
if (s_rand32() % 2)
reg0 = INVALID_P_REG;
else
reg0 = SPECIAL_REG;
} else {
reg0 = SPECIAL_REG;
}
if (!extra0_reg_used) {
if (s_rand32() % 2) {
err = gen_ld_insn_common(insns, &__idx,
EXTRA0_REG,
s_rand64());
} else {
err = gen_mov_insn_common(insns, &__idx, 1,
s_rand32() % 2,
EXTRA0_REG, 0,
s_rand64());
}
if (err < 0) {
return -1;
}
extra0_reg_used = 1;
}
if (s_rand32() % 2) {
reg1 = reg0;
reg0 = EXTRA0_REG;
} else {
reg1 = EXTRA0_REG;
}
err = gen_alu_insn_common(insns, &__idx, is_imm, _64bit,
reg0, reg1, 0, op_code);
if (err < 0) {
return -1;
}
}
*idx = __idx;
return 0;
}
static int gen_mov_insn(struct bpf_insn *insns, int *idx)
{
int __idx = *idx;
int err = 0;
int _64bit = s_rand32() % 2;
int is_imm = s_rand32() % 2;
if (is_imm) {
long imm_v;
if (_64bit)
imm_v = s_rand64();
else
imm_v = s_rand32();
int reg;
int reg_id = s_rand32() % 2;
if (!reg_id) {
if (invalid_reg_used)
if (s_rand32() % 2)
reg = INVALID_P_REG;
else
reg = SPECIAL_REG;
else
reg = SPECIAL_REG;
} else {
reg = EXTRA0_REG;
}
err = gen_mov_insn_common(insns, &__idx, is_imm, _64bit, reg,
0, imm_v);
if (err < 0) {
return -1;
}
if ((reg == EXTRA0_REG) && (!extra0_reg_used)) {
extra0_reg_used = 1;
}
} else {
int reg0, reg1;
int is_src = s_rand32() % 2;
int sort_cases = s_rand32() % 3;
switch (sort_cases) {
case 0:
{
/* INVALID_P_REG and SPECIAL_REG */
reg0 = INVALID_P_REG;
reg1 = SPECIAL_REG;
break;
}
case 1:
{
/* INVALID_P_REG and EXTRA0_REG */
reg0 = INVALID_P_REG;
reg1 = EXTRA0_REG;
break;
}
case 2:
{
/* SPECIAL_REG and EXTRA0_REG */
reg0 = SPECIAL_REG;
reg1 = EXTRA0_REG;
break;
}
default:
{
BUG();
break;
}
}
if (is_src) {
int tmp;
tmp = reg0;
reg0 = reg1;
reg1 = tmp;
}
if ((reg1 == INVALID_P_REG) && (!invalid_reg_used)) {
if (s_rand32() % 2) {
err = gen_ld_insn_common(insns, &__idx,
reg1, s_rand64());
} else {
err = gen_mov_insn_common(insns, &__idx, 1,
s_rand32() % 2,
reg1, 0,
s_rand64());
}
if (err < 0) {
return -1;
}
invalid_reg_used = 1;
}
if ((reg1 == EXTRA0_REG) && (!extra0_reg_used)) {
if (s_rand32() % 2) {
err = gen_ld_insn_common(insns, &__idx,
reg1, s_rand64());
} else {
err = gen_mov_insn_common(insns, &__idx, 1,
s_rand32() % 2,
reg1, 0,
s_rand64());
}
if (err < 0) {
return -1;
}
extra0_reg_used = 1;
}
err = gen_mov_insn_common(insns, &__idx, is_imm, _64bit, reg0,
reg1, 0);
if (err < 0) {
return -1;
}
}
*idx = __idx;
return 0;
}
static int gen_ld_insn(struct bpf_insn *insns, int *idx)
{
int __idx = *idx;
int err = 0;
/* for now, just set EXTRA0_REG */
if (extra0_reg_used) {
return 0;
}
err = gen_ld_insn_common(insns, &__idx, EXTRA0_REG, s_rand64());
if (err < 0) {
return -1;
}
extra0_reg_used = 1;
*idx = __idx;
return 0;
}
static int gen_last_insn(struct bpf_insn *insns, int *idx)
{
if (invalid_reg_used) {
return 0;
}
int __idx = *idx;
if (s_rand32() % 2)
COPY_INSNS(insns, __idx, BPF_MOV64_REG(INVALID_P_REG, SPECIAL_REG));
else
COPY_INSNS(insns, __idx, BPF_MOV32_REG(INVALID_P_REG, SPECIAL_REG));
*idx = __idx;
return 0;
}
static int gen_body1(struct bpf_insn *insns, int *cnt, u32 max_body_insn)
{
int idx = 0;
int err = 0;
invalid_reg_used = 0;
extra0_reg_used = 0;
while (1) {
int insn_idx = rand_range(INSN_GENERATOR_MIN+1, INSN_GENERATOR_MAX);
err = generators[insn_idx](insns, &idx);
if (err < 0)
return -1;
if (idx > max_body_insn) {
err = generators[INSN_GENERATOR_MAX](insns, &idx);
if (err < 0)
return -1;
break;
}
}
*cnt = idx;
return 0;
}
static int insn_body(struct bpf_insn *insns, int *idx, int max,
unsigned long special_val, u32 body1_max)
{
int err = 0;
struct bpf_insn header[BPF_MAXINSNS];
struct bpf_insn body[BPF_MAXINSNS];
int header_cnt = 0;
int body_cnt = 0;
err = gen_body0(header, &header_cnt, special_val);
if (err < 0) {
return -1;
}
err = gen_body1(body, &body_cnt, body1_max);
if (err < 0) {
return -1;
}
unsigned insn_cnt = header_cnt + body_cnt;
struct bpf_insn this_insns[insn_cnt];
for (unsigned i = 0; i < header_cnt; i++) {
this_insns[i] = header[i];
}
for (unsigned i = 0; i < body_cnt; i++) {
this_insns[i+header_cnt] = body[i];
}
err = insn_add(insns, idx, max, this_insns, insn_cnt);
if (err < 0) {
return -1;
}
return 0;
}
static int insn_alu_map_ptr(struct bpf_insn *insns, int *idx, int max)
{
int err = 0;
struct bpf_insn this_insns[] = {
BPF_ALU64_REG(BPF_SUB, CORRUPT_REG, INVALID_P_REG),
};
err = insn_add(insns, idx, max, this_insns, ARRAY_CNT(this_insns));
if (err < 0) {
return -1;
}
return 0;
}
static int insn_write_mem(struct bpf_insn *insns, int *idx, int max)
{
int err = 0;
struct bpf_insn this_insns[] = {
BPF_LDX_MEM(BPF_DW, LEAKED_V_REG, CORRUPT_REG, 0),
BPF_STX_MEM(BPF_DW, STORAGE_REG, LEAKED_V_REG, 8),
BPF_MOV64_IMM(BPF_REG_0, 1),
};
err = insn_add(insns, idx, max, this_insns, ARRAY_CNT(this_insns));
if (err < 0) {
return -1;
}
return 0;
}
static int insn_exit(struct bpf_insn *insns, int *idx, int max)
{
struct bpf_insn this_insns[] = {
BPF_EXIT_INSN(),
};
return insn_add(insns, idx, max, this_insns, ARRAY_CNT(this_insns));
}
static char *sample_header = ""
"#include <stdio.h>\n"
"#include <stdlib.h>\n"
"#include <string.h>\n"
"#include <stdint.h>\n"
"#include <errno.h>\n"
"#include <assert.h>\n"
"#include <unistd.h>\n"
"#include <sys/types.h>\n"
"#include <sys/wait.h>\n"
"#include <sys/time.h>\n"
"#include <fcntl.h>\n"
"#include <sys/syscall.h>\n"
"#include <sys/ioctl.h>\n"
"#include <sys/stat.h>\n"
"#include <sys/socket.h>\n"
"#include <signal.h>\n"
"#include <netinet/in.h>\n"
"#include <arpa/inet.h>\n"
"#include <linux/bpf.h>\n"
"#include <linux/bpf_common.h>\n"
"#include <sys/prctl.h>\n"
"\n"
"enum qemu_fuzzlib_inst_res {\n"
" QEMU_FUZZLIB_INST_INVALID = -1,\n"
" QEMU_FUZZLIB_INST_NOT_TESTED = 0,\n"
" QEMU_FUZZLIB_INST_VALID,\n"
" QEMU_FUZZLIB_INST_BOOM,\n"
"};\n"
"\n"
"typedef __s8 s8;\n"
"typedef __s16 s16;\n"
"typedef __s32 s32;\n"
"typedef __s64 s64;\n"
"typedef __u8 u8;\n"
"typedef __u16 u16;\n"
"typedef __u32 u32;\n"
"typedef __u64 u64;\n"
"\n"
"struct xmsg {\n"
" unsigned long special_value;\n"
" unsigned long insn_cnt;\n"
" struct bpf_insn insns[BPF_MAXINSNS];\n"
"};\n"
"\n"
"#ifndef BPF_JMP32\n"
"#define BPF_JMP32 0x06\n"
"#endif\n"
"\n"
"/* ArgX, context and stack frame pointer register positions. Note,\n"
" * Arg1, Arg2, Arg3, etc are used as argument mappings of function\n"
" * calls in BPF_CALL instruction.\n"
" */\n"
"#define BPF_REG_ARG1 BPF_REG_1\n"
"#define BPF_REG_ARG2 BPF_REG_2\n"
"#define BPF_REG_ARG3 BPF_REG_3\n"
"#define BPF_REG_ARG4 BPF_REG_4\n"
"#define BPF_REG_ARG5 BPF_REG_5\n"
"#define BPF_REG_CTX BPF_REG_6\n"
"#define BPF_REG_FP BPF_REG_10\n"
"\n"
"/* Additional register mappings for converted user programs. */\n"
"#define BPF_REG_A BPF_REG_0\n"
"#define BPF_REG_X BPF_REG_7\n"
"#define BPF_REG_TMP BPF_REG_2 /* scratch reg */\n"
"#define BPF_REG_D BPF_REG_8 /* data, callee-saved */\n"
"#define BPF_REG_H BPF_REG_9 /* hlen, callee-saved */\n"
"\n"
"/* Kernel hidden auxiliary/helper register. */\n"
"#define BPF_REG_AX MAX_BPF_REG\n"
"#define MAX_BPF_EXT_REG (MAX_BPF_REG + 1)\n"
"#define MAX_BPF_JIT_REG MAX_BPF_EXT_REG\n"
"\n"
"/* unused opcode to mark special call to bpf_tail_call() helper */\n"
"#define BPF_TAIL_CALL 0xf0\n"
"\n"
"/* unused opcode to mark call to interpreter with arguments */\n"
"#define BPF_CALL_ARGS 0xe0\n"
"\n"
"/* As per nm, we expose JITed images as text (code) section for\n"
" * kallsyms. That way, tools like perf can find it to match\n"
" * addresses.\n"
" */\n"
"#define BPF_SYM_ELF_TYPE 't'\n"
"\n"
"/* BPF program can access up to 512 bytes of stack space. */\n"
"#define MAX_BPF_STACK 512\n"
"\n"
"/* Helper macros for filter block array initializers. */\n"
"\n"
"/* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */\n"
"\n"
"#define BPF_ALU64_REG(OP, DST, SRC) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = 0 })\n"
"\n"
"#define BPF_ALU32_REG(OP, DST, SRC) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_OP(OP) | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = 0 })\n"
"\n"
"/* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */\n"
"\n"
"#define BPF_ALU64_IMM(OP, DST, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"#define BPF_ALU32_IMM(OP, DST, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_OP(OP) | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"/* Endianess conversion, cpu_to_{l,b}e(), {l,b}e_to_cpu() */\n"
"\n"
"#define BPF_ENDIAN(TYPE, DST, LEN) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_END | BPF_SRC(TYPE), \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = LEN })\n"
"\n"
"/* Short form of mov, dst_reg = src_reg */\n"
"\n"
"#define BPF_MOV64_REG(DST, SRC) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU64 | BPF_MOV | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = 0 })\n"
"\n"
"#define BPF_MOV32_REG(DST, SRC) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_MOV | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = 0 })\n"
"\n"
"/* Short form of mov, dst_reg = imm32 */\n"
"\n"
"#define BPF_MOV64_IMM(DST, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU64 | BPF_MOV | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"#define BPF_MOV32_IMM(DST, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_MOV | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"/* Special form of mov32, used for doing explicit zero extension on dst. */\n"
"#define BPF_ZEXT_REG(DST) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_MOV | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = DST, \\\n"
" .off = 0, \\\n"
" .imm = 1 })\n"
"\n"
"/* BPF_LD_IMM64 macro encodes single 'load 64-bit immediate' insn */\n"
"#define BPF_LD_IMM64(DST, IMM) \\\n"
" BPF_LD_IMM64_RAW(DST, 0, IMM)\n"
"\n"
"#define BPF_LD_IMM64_RAW(DST, SRC, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_LD | BPF_DW | BPF_IMM, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = (__u32) (IMM) }), \\\n"
" ((struct bpf_insn) { \\\n"
" .code = 0, /* zero is reserved opcode */ \\\n"
" .dst_reg = 0, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = ((__u64) (IMM)) >> 32 })\n"
"\n"
"/* pseudo BPF_LD_IMM64 insn used to refer to process-local map_fd */\n"
"#define BPF_LD_MAP_FD(DST, MAP_FD) \\\n"
" BPF_LD_IMM64_RAW(DST, BPF_PSEUDO_MAP_FD, MAP_FD)\n"
"\n"
"/* Short form of mov based on type, BPF_X: dst_reg = src_reg, BPF_K: dst_reg = imm32 */\n"
"\n"
"#define BPF_MOV64_RAW(TYPE, DST, SRC, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU64 | BPF_MOV | BPF_SRC(TYPE), \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"#define BPF_MOV32_RAW(TYPE, DST, SRC, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ALU | BPF_MOV | BPF_SRC(TYPE), \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"/* Direct packet access, R0 = *(uint *) (skb->data + imm32) */\n"
"\n"
"#define BPF_LD_ABS(SIZE, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_LD | BPF_SIZE(SIZE) | BPF_ABS, \\\n"
" .dst_reg = 0, \\\n"
" .src_reg = 0, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"/* Indirect packet access, R0 = *(uint *) (skb->data + src_reg + imm32) */\n"
"\n"
"#define BPF_LD_IND(SIZE, SRC, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_LD | BPF_SIZE(SIZE) | BPF_IND, \\\n"
" .dst_reg = 0, \\\n"
" .src_reg = SRC, \\\n"
" .off = 0, \\\n"
" .imm = IMM })\n"
"\n"
"/* Memory load, dst_reg = *(uint *) (src_reg + off16) */\n"
"\n"
"#define BPF_LDX_MEM(SIZE, DST, SRC, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_LDX | BPF_SIZE(SIZE) | BPF_MEM, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Memory store, *(uint *) (dst_reg + off16) = src_reg */\n"
"\n"
"#define BPF_STX_MEM(SIZE, DST, SRC, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_STX | BPF_SIZE(SIZE) | BPF_MEM, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Atomic memory add, *(uint *)(dst_reg + off16) += src_reg */\n"
"\n"
"#define BPF_STX_XADD(SIZE, DST, SRC, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_STX | BPF_SIZE(SIZE) | BPF_XADD, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Memory store, *(uint *) (dst_reg + off16) = imm32 */\n"
"\n"
"#define BPF_ST_MEM(SIZE, DST, OFF, IMM) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_ST | BPF_SIZE(SIZE) | BPF_MEM, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = OFF, \\\n"
" .imm = IMM })\n"
"\n"
"/* Conditional jumps against registers, if (dst_reg 'op' src_reg) goto pc + off16 */\n"
"\n"
"#define BPF_JMP_REG(OP, DST, SRC, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP | BPF_OP(OP) | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Conditional jumps against immediates, if (dst_reg 'op' imm32) goto pc + off16 */\n"
"\n"
"#define BPF_JMP_IMM(OP, DST, IMM, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP | BPF_OP(OP) | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = OFF, \\\n"
" .imm = IMM })\n"
"\n"
"/* Like BPF_JMP_REG, but with 32-bit wide operands for comparison. */\n"
"\n"
"#define BPF_JMP32_REG(OP, DST, SRC, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP32 | BPF_OP(OP) | BPF_X, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = SRC, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Like BPF_JMP_IMM, but with 32-bit wide operands for comparison. */\n"
"\n"
"#define BPF_JMP32_IMM(OP, DST, IMM, OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP32 | BPF_OP(OP) | BPF_K, \\\n"
" .dst_reg = DST, \\\n"
" .src_reg = 0, \\\n"
" .off = OFF, \\\n"
" .imm = IMM })\n"
"\n"
"/* Unconditional jumps, goto pc + off16 */\n"
"\n"
"#define BPF_JMP_A(OFF) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP | BPF_JA, \\\n"
" .dst_reg = 0, \\\n"
" .src_reg = 0, \\\n"
" .off = OFF, \\\n"
" .imm = 0 })\n"
"\n"
"/* Relative call */\n"
"\n"
"#define BPF_CALL_REL(TGT) \\\n"
" ((struct bpf_insn) { \\\n"
" .code = BPF_JMP | BPF_CALL, \\\n"
" .dst_reg = 0, \\\n"
" .src_reg = BPF_PSEUDO_CALL, \\\n"
" .off = 0, \\\n"
" .imm = TGT })\n"