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processor.qsf
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processor.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 19:15:53 April 08, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# processor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX V"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY DUT
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:15:53 APRIL 08, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "Testbench-final" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME Testbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Testbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Testbench -section_id Testbench
set_global_assignment -name EDA_TEST_BENCH_NAME "Testbench-RegisterBank" -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id "Testbench-RegisterBank"
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Testbench -section_id "Testbench-RegisterBank"
set_global_assignment -name TEXT_FILE TRACEFILE.txt
set_global_assignment -name VHDL_FILE processor.vhdl
set_global_assignment -name VHDL_FILE IR/IR.vhdl
set_global_assignment -name VHDL_FILE Controller/controller.vhdl
set_global_assignment -name VHDL_FILE ALU/fa.vhdl
set_global_assignment -name VHDL_FILE ALU/adder_4.vhdl
set_global_assignment -name VHDL_FILE ALU/adder_16.vhdl
set_global_assignment -name VHDL_FILE RAM/RAM.vhdl
set_global_assignment -name VHDL_FILE ALU/ALU.vhdl
set_global_assignment -name VHDL_FILE registers/flags.vhdl
set_global_assignment -name VHDL_FILE incrementer/incrementer.vhdl
set_global_assignment -name VHDL_FILE register_bank/register_bank.vhdl
set_global_assignment -name VHDL_FILE registers/reg.vhdl
set_global_assignment -name VHDL_FILE datapath/datapath.vhdl
set_global_assignment -name VHDL_FILE Testbench.vhdl
set_global_assignment -name VHDL_FILE DUT.vhdl
set_global_assignment -name VHDL_FILE micro_controller.vhdl
set_global_assignment -name EDA_TEST_BENCH_FILE ALU/TRACEFILE.txt -section_id Testbench
set_global_assignment -name EDA_TEST_BENCH_FILE ALU/Testbench.vhdl -section_id Testbench
set_global_assignment -name EDA_TEST_BENCH_FILE RegisterBank/TRACEFILE.txt -section_id "Testbench-RegisterBank"
set_global_assignment -name EDA_TEST_BENCH_FILE RegisterBank/Testbench.vhdl -section_id "Testbench-RegisterBank"
set_global_assignment -name EDA_TEST_BENCH_NAME "Testbench-final" -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id "Testbench-final"
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Testbench -section_id "Testbench-final"
set_global_assignment -name EDA_TEST_BENCH_FILE TRACEFILE.txt -section_id "Testbench-final"
set_global_assignment -name EDA_TEST_BENCH_FILE Testbench.vhdl -section_id "Testbench-final"