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Fix marker sampling, add RData state and add support for JTAG-to-SWD sequence. #4

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@nezza nezza commented May 9, 2022

Hello,

This PR should fix #2 and #3 (or at least improve behavior in 90% of cases).
Also, so far the analyzer always indicated the data-phase as "WData" phase, even for reads. This PR adds an "RData" phase that is used for reads.

This commit also adds a JTAG-to-SWD sequence detector, so that the line resets are easier to read.

Correct sampling edge (purple = previously, yellow = this PR):
Screenshot 2022-05-09 at 11 47 58
Screenshot 2022-05-09 at 11 47 36

RData vs WData (purple = previously, yellow = this PR):
Screenshot 2022-05-09 at 11 46 57

JTAG to SWD sequence (purple = previously, yellow = this PR):

Screenshot 2022-05-09 at 11 48 17

Screenshot 2022-05-09 at 11 48 35

Let me know what you think.

Thanks,
Thomas

@nezza nezza closed this May 9, 2022
@nezza nezza reopened this May 9, 2022
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nezza commented Aug 15, 2023

Bringing this up again :)

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Bit values are annotated on wrong clock edge
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