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Disable SV generation when running VHDL code generation #204

Closed Answered by taichi-ishitani
SzymonHitachi asked this question in Q&A
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Hi @SzymonHitachi ,
You can use --enable option for this purspose.

$ rggen -c config.yaml --enable vhdl regmap.yaml

For this example, RgGen will generate VHDL only.

$ rggen -c config.yaml --enable vhdl,markdown,c_header regmap.yaml

For this example, RgGen will generate VHDL, Markdown and C header files.

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@SzymonHitachi
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@SzymonHitachi
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