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arm-dis.c
6852 lines (6233 loc) · 240 KB
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arm-dis.c
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/* Instruction printing code for the ARM
Copyright (C) 1994-2017 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modification by James G. Smith (jsmith@cygnus.co.uk)
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "disas-asm.h"
#include "opcode-arm.h"
// #include "opcode/arm.h"
#include "opintl.h"
// #include "safe-ctype.h"
#ifndef _MSC_VER
#include "libiberty.h"
#else
#include <stdlib.h>
#define XNEWVEC(T, N) ((T *) malloc (sizeof (T) * (N)))
#define XCNEWVEC(T, N) ((T *) calloc ((N), sizeof (T)))
#define XNEW(T) ((T *) malloc (sizeof (T)))
#define ARRAY_SIZE _countof
#endif
#include "floatformat.h"
/* FIXME: This shouldn't be done here. */
// #include "coff/internal.h"
// #include "libcoff.h"
// #include "elf-bfd.h"
// #include "elf/internal.h"
// #include "elf/arm.h"
// #include "mach-o.h"
#define abort() exit(1)
/* FIXME: Belongs in global header. */
#ifndef strneq
#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
#endif
/* Cached mapping symbol state. */
enum map_type
{
MAP_ARM,
MAP_THUMB,
MAP_DATA
};
struct arm_private_data
{
/* The features to use when disassembling optional instructions. */
arm_feature_set features;
/* Whether any mapping symbols are present in the provided symbol
table. -1 if we do not know yet, otherwise 0 or 1. */
int has_mapping_symbols;
/* Track the last type (although this doesn't seem to be useful) */
enum map_type last_type;
/* Tracking symbol table information */
int last_mapping_sym;
bfd_vma last_mapping_addr;
};
struct opcode32
{
arm_feature_set arch; /* Architecture defining this insn. */
unsigned long value; /* If arch is 0 then value is a sentinel. */
unsigned long mask; /* Recognise insn if (op & mask) == value. */
const char * assembler; /* How to disassemble this insn. */
};
struct opcode16
{
arm_feature_set arch; /* Architecture defining this insn. */
unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
const char *assembler; /* How to disassemble this insn. */
};
/* print_insn_coprocessor recognizes the following format control codes:
%% %
%c print condition code (always bits 28-31 in ARM mode)
%q print shifter argument
%u print condition code (unconditional in ARM mode,
UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitfield>c print as a condition code (for vsel)
%<bitfield>r print as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
%<bitfield>ru as %<>r but each u register must be unique.
%<bitfield>d print the bitfield in decimal
%<bitfield>k print immediate for VFPv3 conversion instruction
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>f print a floating point constant if >7 else a
floating point register
%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
%<bitfield>g print as an iWMMXt 64-bit register
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>V print as a NEON D or Q register
%<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
%z<code> print a double precision VFP reg
Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
%l like 'A' except use byte offsets for 'B' & 'H'
versions.
%i print 5-bit immediate in bits 8,3..0
(print "32" when 0)
%r print register offset address for wldt/wstr instruction. */
enum opcode_sentinel_enum
{
SENTINEL_IWMMXT_START = 1,
SENTINEL_IWMMXT_END,
SENTINEL_GENERIC_START
} opcode_sentinels;
#define UNDEFINED_INSTRUCTION " ; <UNDEFINED> instruction: %0-31x"
#define UNPREDICTABLE_INSTRUCTION " ; <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
static const struct opcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
"mia%c acc0, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
"miaph%c acc0, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c acc0, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00fff, "mar%c acc0, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00fff, "mra%c %12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
{ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
{ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c %16-19g, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c %12-15r, %0-2d"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c %12-15r, %16-19g, %0-2d"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c %16-19g, %12-15r, %0-2d"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c %16-19G, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00ff0, "tmcrr%c %0-3g, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c %5-8g, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0e10, "tmia%c %5-8g, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0e10, "tmiaph%c %5-8g, %0-3r, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c %12-15r, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100110, 0x0ff00ff0, "tmrc%c %12-15r, %16-19G"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00ff0, "tmrrc%c %12-15r, %16-19r, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130150, 0x0f3f0fff, "torc%22-23w%c %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000180, 0x0f000ff0, "wadd%20-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000020, 0x0f800ff0, "waligni%c %12-15g, %16-19g, %0-3g, %20-22d"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200000, 0x0fe00ff0, "wand%20'n%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc500100, 0xfe500f00, "wldrd %12-15g, %r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc100100, 0xfe500f00, "wldrw %12-15G, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c100000, 0x0e100e00, "wldr%L%c %12-15g, %l"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f100fe0, "wmerge%c %12-15g, %16-19g, %0-3g, %21-23d"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800120, 0x0f800ff0,
"wmiaw%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0eb000c0, 0x0ff00ff0, "wmulwl%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000a0, 0x0f800ff0,
"wqmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000000, 0x0ff00ff0, "wor%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe300040, 0xff300ef0, "wror%22-23w %12-15g, %16-19g, %i"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300140, 0x0f300ff0, "wror%22-23wg%c %12-15g, %16-19g, %0-3G"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001e0, 0x0f000ff0, "wshufh%c %12-15g, %16-19g, %Z"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe100040, 0xff300ef0, "wsll%22-23w %12-15g, %16-19g, %i"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe000040, 0xff300ef0, "wsra%22-23w %12-15g, %16-19g, %i"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe200040, 0xff300ef0, "wsrl%22-23w %12-15g, %16-19g, %i"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc400100, 0xfe500f00, "wstrd %12-15g, %r"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc000100, 0xfe500f00, "wstrw %12-15G, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c000000, 0x0e100e00, "wstr%L%c %12-15g, %l"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c %12-15g, %16-19g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100000, 0x0ff00ff0, "wxor%c %12-15g, %16-19g, %0-3g"},
{ARM_FEATURE_CORE_LOW (0),
SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions. */
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ee08100, 0x0ff08f10, "urd%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef08100, 0x0ff08f10, "nrm%c%P%R %12-14f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200110, 0x0fff0fff, "wfs%c %12-15r"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300110, 0x0fff0fff, "rfs%c %12-15r"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400110, 0x0fff0fff, "wfc%c %12-15r"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500110, 0x0fff0fff, "rfc%c %12-15r"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c000200, 0x0e100f00, "sfm%c %12-14f, %F, %A"},
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c %12-14f, %F, %A"},
/* ARMv8-M Mainline Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec300a00, 0xfff0ffff, "vlldm %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec200a00, 0xfff0ffff, "vlstm %16-19r"},
/* Register load/store. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d200b00, 0x0fb00f01, "vstmdb%c %16-19r!, %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d300b00, 0x0fb00f01, "vldmdb%c %16-19r!, %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c800b00, 0x0f900f01, "vstmia%c %16-19r%21'!, %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0cbd0b00, 0x0fbf0f01, "vpop%c %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c900b00, 0x0f900f01, "vldmia%c %16-19r%21'!, %B"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d000b00, 0x0f300f00, "vstr%c %12-15,22D, %A"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d100b00, 0x0f300f00, "vldr%c %12-15,22D, %A"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d2d0a00, 0x0fbf0f00, "vpush%c %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200a00, 0x0fb00f00, "vstmdb%c %16-19r!, %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300a00, 0x0fb00f00, "vldmdb%c %16-19r!, %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800a00, 0x0f900f00, "vstmia%c %16-19r%21'!, %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0cbd0a00, 0x0fbf0f00, "vpop%c %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900a00, 0x0f900f00, "vldmia%c %16-19r%21'!, %y3"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d000a00, 0x0f300f00, "vstr%c %y1, %A"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c %y1, %A"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c %16-19r!, %z3 ;@ Deprecated"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300b01, 0x0fb00f01, "fldmdbx%c %16-19r!, %z3 ;@ Deprecated"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800b01, 0x0f900f01, "fstmiax%c %16-19r%21'!, %z3 ;@ Deprecated"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900b01, 0x0f900f01, "fldmiax%c %16-19r%21'!, %z3 ;@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b10, 0x0ff00f70, "vdup%c.32 %16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b30, 0x0ff00f70, "vdup%c.16 %16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b10, 0x0ff00f70, "vdup%c.32 %16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b30, 0x0ff00f70, "vdup%c.16 %16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ec00b10, 0x0ff00f70, "vdup%c.8 %16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ee00b10, 0x0ff00f70, "vdup%c.8 %16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c400b10, 0x0ff00fd0, "vmov%c %0-3,5D, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b10, 0x0fd00f70, "vmov%c.32 %16-19,7D[%21d], %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b10, 0x0f500f70, "vmov%c.32 %12-15r, %16-19,7D[%21d]"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b30, 0x0fd00f30, "vmov%c.16 %16-19,7D[%6,21d], %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16 %12-15r, %16-19,7D[%6,21d]"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e400b10, 0x0fd00f10, "vmov%c.8 %16-19,7D[%5,6,21d], %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8 %12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16 %z1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64 %y1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32 %y1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0fff0fff, "vmsr%c fpsid, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee10a10, 0x0fff0fff, "vmsr%c fpscr, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee60a10, 0x0fff0fff, "vmsr%c mvfr1, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee70a10, 0x0fff0fff, "vmsr%c mvfr0, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c fpexc, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee90a10, 0x0fff0fff, "vmsr%c fpinst, %12-15r @ Impl def"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eea0a10, 0x0fff0fff, "vmsr%c fpinst2, %12-15r @ Impl def"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0fff0fff, "vmrs%c %12-15r, fpsid"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef1fa10, 0x0fffffff, "vmrs%c APSR_nzcv, fpscr"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef10a10, 0x0fff0fff, "vmrs%c %12-15r, fpscr"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef60a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr1"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef70a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c %12-15r, fpexc"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef90a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst @ Impl def"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0efa0a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst2 @ Impl def"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b10, 0x0fd00fff, "vmov%c.32 %z2[%21d], %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b10, 0x0fd00fff, "vmov%c.32 %12-15r, %z2[%21d]"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c <impl def %16-19x>, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0ff00fff, "vmrs%c %12-15r, <impl def %16-19x>"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a10, 0x0ff00f7f, "vmov%c %y2, %12-15r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c %12-15r, %y2"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32 %y1, #0.0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64 %z1, #0.0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32 %z1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64 %y1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32 %z1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26 %z1, %z1, %5,0-3k"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64 %y1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32 %y1, %y1, %5,0-3k"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64 %z1, %z1, %5,0-3k"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c %12-15r, %16-19r, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32 %y1, %0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64 %z1, %0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c %y4, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400b10, 0x0ff00fd0, "vmov%c %z0, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c500a10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %y4"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a00, 0x0fb00f50, "vmla%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a40, 0x0fb00f50, "vmls%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b00, 0x0fb00f50, "vmla%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b40, 0x0fb00f50, "vmls%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a00, 0x0fb00f50, "vnmls%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a40, 0x0fb00f50, "vnmla%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b00, 0x0fb00f50, "vnmls%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b40, 0x0fb00f50, "vnmla%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a00, 0x0fb00f50, "vmul%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a40, 0x0fb00f50, "vnmul%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b00, 0x0fb00f50, "vmul%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b40, 0x0fb00f50, "vnmul%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a00, 0x0fb00f50, "vadd%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a40, 0x0fb00f50, "vsub%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b00, 0x0fb00f50, "vadd%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b40, 0x0fb00f50, "vsub%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e800a00, 0x0fb00f50, "vdiv%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64 %z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c mvf%16-19d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c %12-15r, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c mvd%16-19d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c %12-15r, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c mvd%16-19d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c %12-15r, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c mvdx%16-19d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c %12-15r, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c mvdx%16-19d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c %12-15r, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c mvax%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c mvfx%12-15d, mvax%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c mvax%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c mvfx%12-15d, mvax%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c mvax%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c mvfx%12-15d, mvax%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c mvax%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c mvfx%12-15d, mvax%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c mvax%12-15d, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c mvdx%12-15d, mvax%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c dspsc, mvdx%12-15d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c mvdx%12-15d, dspsc"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c mvf%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c mvd%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c mvd%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c mvf%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c mvf%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c mvd%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c mvf%12-15d, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c mvd%12-15d, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c mvfx%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c mvfx%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c mvfx%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c mvfx%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c mvfx%16-19d, mvfx%0-3d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c mvdx%16-19d, mvdx%0-3d, %12-15r"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c mvfx%12-15d, mvfx%16-19d, %I"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c mvdx%12-15d, mvdx%16-19d, %I"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c %12-15r, mvf%16-19d, mvf%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c %12-15r, mvd%16-19d, mvd%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c %12-15r, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c %12-15r, mvdx%16-19d, mvdx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c mvf%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c mvd%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c mvf%12-15d, mvf%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c mvd%12-15d, mvd%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c mvfx%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c mvdx%12-15d, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c mvfx%12-15d, mvfx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c mvdx%12-15d, mvdx%16-19d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* VFP Fused multiply add instructions. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b00, 0x0fb00f50, "vfma%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a40, 0x0fb00f50, "vfms%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b40, 0x0fb00f50, "vfms%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a40, 0x0fb00f50, "vfnma%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b40, 0x0fb00f50, "vfnma%c.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a00, 0x0fb00f50, "vfnms%c.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b00, 0x0fb00f50, "vfnms%c.f64 %z1, %z2, %z0"},
/* FP v5. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a00, 0xffb00f50, "vmaxnm%u.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b00, 0xffb00f50, "vmaxnm%u.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a40, 0xffb00f50, "vminnm%u.f32 %y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b40, 0xffb00f50, "vminnm%u.f64 %z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64 %y1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64 %z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32 %y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64 %z1, %z0"},
/* Generic coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c400000, 0x0ff00000, "mcrr%c %8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
"mrrc%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
"cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
"mrc%c %8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
"mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
"mcr%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c000000, 0x0e100000, "stc%22'l%c %8-11d, cr%12-15d, %A"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c100000, 0x0e100000, "ldc%22'l%c %8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
"mrrc2%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
"mcrr2%c %8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc800800, 0xfeb00f10, "vcadd%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc900800, 0xfeb00f10, "vcadd%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe000800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe200800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20?21%20?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe800800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfea00800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20?21%20?780"},
/* V5 coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c %8-11d, cr%12-15d, %A"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc000000, 0xfe100000, "stc2%22'l%c %8-11d, cr%12-15d, %A"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
"cdp2%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
"mcr2%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
"mrc2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300900, 0x0fb00f50, "vadd%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16 %y1, #0.0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16 %y1, %y1, %5,0-3k"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e800900, 0x0fb00f50, "vdiv%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00900, 0x0fb00f50, "vfma%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00940, 0x0fb00f50, "vfms%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900940, 0x0fb00f50, "vfnma%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900900, 0x0fb00f50, "vfnms%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00ac0, 0xffbf0fd0, "vins.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d100900, 0x0f300f00, "vldr%c.16 %y1, %A"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d000900, 0x0f300f00, "vstr%c.16 %y1, %A"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800900, 0xffb00f50, "vmaxnm%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800940, 0xffb00f50, "vminnm%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000900, 0x0fb00f50, "vmla%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000940, 0x0fb00f50, "vmls%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100910, 0x0ff00f7f, "vmov%c.f16 %12-15r, %y2"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16 %y2, %12-15r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xeb00900, 0x0fb00ff0, "vmov%c.f16 %y1, %0-3,16-19E"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb10940, 0x0fbf0fd0, "vneg%c.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100940, 0x0fb00f50, "vnmla%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100900, 0x0fb00f50, "vnmls%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200940, 0x0fb00f50, "vnmul%c.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16 %y1, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe000900, 0xff800f50, "vsel%20-21c%u.f16 %y1, %y2, %y0"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16 %y1, %y0"},