/
arcompact-dis.c
3938 lines (3444 loc) · 92.6 KB
/
arcompact-dis.c
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/* Instruction printing code for the ARC.
Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
Copyright 2008-2012 Synopsys Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <ctype.h>
#include <stdarg.h>
#include <ansidecl.h>
#include <string.h>
#include "disas-asm.h"
#include "arc.h"
#include "arc-ext.h"
#include "arc-dis.h"
#include "arcompact-dis.h"
#include "elf-bfd.h"
#include "r_types.h"
/*
warning: implicit declaration of function `eprintf'
if dbg is 1 then this definition is required
*/
static bfd_vma bfd_getm32 (unsigned int);
static bfd_vma bfd_getm32_ac (unsigned int) ATTRIBUTE_UNUSED;
#ifndef dbg
#define dbg (0)
#endif
/*
Ravi:
: undefined reference to `eprintf'
if dbg is 1 then this definition is required
*/
#undef _NELEM
#define _NELEM(ary) (sizeof(ary) / sizeof(ary[0]))
#define BIT(word,n) ((word) & (1 << n))
/* START ARC LOCAL */
#define BITS(word,s,e) (((word) << (sizeof(word)*8-1 - e)) >> (s+(sizeof(word)*8-1 - e)))
/* END ARC LOCAL */
#define OPCODE(word) (BITS ((word), 27, 31))
#define FIELDA(word) (BITS ((word), 0, 5))
#define FIELDb(word) (BITS ((word), 24, 26))
#define FIELDB(word) (BITS ((word), 12, 14))
#define FIELDC(word) (BITS ((word), 6, 11))
#define OPCODE_AC(word) (BITS ((word), 11, 15))
#define FIELDA_AC(word) (BITS ((word), 0, 2))
#define FIELDB_AC(word) (BITS ((word), 8, 10))
#define FIELDC_AC(word) (BITS ((word), 5, 7))
#define FIELDU_AC(word) (BITS ((word), 0, 4))
/*
* FIELDS_AC is the 11-bit signed immediate value used for
* GP-relative instructions.
*/
#define FIELDS_AC(word) (BITS (((signed int) word), 0, 8))
/*
* FIELDD is signed in all of its uses, so we make sure argument is
* treated as signed for bit shifting purposes.
*/
#define FIELDD(word) (BITS (((signed int) word), 16, 23))
/*
* FIELDD9 is the 9-bit signed immediate value used for
* load/store instructions.
*/
#define FIELDD9(word) ((BITS(((signed int)word),15,15) << 8) | (BITS((word),16,23)))
/*
* FIELDS is the 12-bit signed immediate value
*/
#define FIELDS(word) ((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11))) \
/*
* FIELD S9 is the 9-bit signed immediate value used for
* bbit0/bbit instruction
*/
#define FIELDS9(word) (((BITS(((signed int)word),15,15) << 7) | (BITS((word),17,23))) << 1)
#define FIELDS9_FLAG(word) (((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11))) )
#define PUT_NEXT_WORD_IN(a) { \
if (is_limm==1 && !NEXT_WORD(1)) \
mwerror(state, "Illegal limm reference in last instruction!\n"); \
if (info->endian == BFD_ENDIAN_LITTLE) { \
a = ((state->words[1] & 0xff00) | (state->words[1] & 0xff)) << 16; \
a |= ((state->words[1] & 0xff0000) | (state->words[1] & 0xff000000)) >> 16; \
} \
else { \
a = state->words[1]; \
} \
}
#define CHECK_NULLIFY() do{ \
state->nullifyMode = BITS(state->words[0],5,5); \
}while(0)
#define CHECK_COND_NULLIFY() do { \
state->nullifyMode = BITS(state->words[0],5,5); \
cond = BITS(state->words[0],0,4); \
}while(0)
#define CHECK_FLAG_COND_NULLIFY() do{ \
if (is_shimm == 0) { \
flag = BIT(state->words[0],15); \
state->nullifyMode = BITS(state->words[0],5,5); \
cond = BITS(state->words[0],0,4); \
} \
}while(0)
#define CHECK_FLAG_COND() { \
if (is_shimm == 0) { \
flag = BIT(state->words[0],15); \
cond = BITS(state->words[0],0,4); \
} \
}
#define CHECK_FLAG() { \
flag = BIT(state->words[0],15); \
}
#define CHECK_COND() { \
if (is_shimm == 0) { \
cond = BITS(state->words[0],0,4); \
} \
}
#define CHECK_FIELD(field) { \
if (field == 62) { \
is_limm++; \
field##isReg = 0; \
PUT_NEXT_WORD_IN(field); \
} \
}
#define CHECK_FIELD_A() { \
fieldA = FIELDA(state->words[0]); \
if (fieldA == 62) { \
fieldAisReg = 0; \
fieldA = 0; \
} \
}
#define FIELD_B() { \
fieldB = (FIELDB(state->words[0]) << 3);\
fieldB |= FIELDb(state->words[0]); \
if (fieldB == 62) { \
fieldBisReg = 0; \
fieldB = 0; \
} \
}
#define FIELD_C() { \
fieldC = FIELDC(state->words[0]); \
if (fieldC == 62) { \
fieldCisReg = 0; \
} \
}
/********** Aurora SIMD ARC 8 - bit constant **********/
#define FIELD_U8() { \
\
fieldC = BITS(state->words[0],15,16);\
fieldC = fieldC <<6; \
fieldC |= FIELDC(state->words[0]); \
fieldCisReg = 0; \
}
#define CHECK_FIELD_B() { \
fieldB = (FIELDB(state->words[0]) << 3);\
fieldB |= FIELDb(state->words[0]); \
CHECK_FIELD(fieldB); \
}
#define CHECK_FIELD_C() { \
fieldC = FIELDC(state->words[0]); \
CHECK_FIELD(fieldC); \
}
#define FIELD_C_S() { \
fieldC_S = (FIELDC_S(state->words[0]) << 3); \
}
#define FIELD_B_S() { \
fieldB_S = (FIELDB_S(state->words[0]) << 3); \
}
#define CHECK_FIELD_H_AC() { \
fieldC = ((FIELDA_AC(state->words[0])) << 3); \
fieldC |= FIELDC_AC(state->words[0]); \
CHECK_FIELD(fieldC); \
}
#define FIELD_H_AC() { \
fieldC = ((FIELDA_AC(state->words[0])) << 3); \
fieldC |= FIELDC_AC(state->words[0]); \
if (fieldC > 60) { \
fieldCisReg = 0; \
fieldC = 0; \
} \
}
#define FIELD_C_AC() { \
fieldC = FIELDC_AC(state->words[0]); \
if (fieldC > 3) { \
fieldC += 8; \
} \
}
#define FIELD_B_AC() { \
fieldB = FIELDB_AC(state->words[0]); \
if (fieldB > 3) { \
fieldB += 8; \
} \
}
#define FIELD_A_AC() { \
fieldA = FIELDA_AC(state->words[0]); \
if (fieldA > 3) { \
fieldA += 8; \
} \
}
#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
#define IS_REG(x) (field##x##isReg)
#define IS_SIMD_128_REG(x) (usesSimdReg##x == 1)
#define IS_SIMD_16_REG(x) (usesSimdReg##x == 2)
#define IS_SIMD_DATA_REG(x) (usesSimdReg##x == 3)
#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",", [","",",[")
#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,", ","]",", ","]")
#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,", ","",", ","")
#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",", ","",", ")
#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat(formatString, \
(IS_SIMD_128_REG(x) ? cb1"%S"ca1: \
IS_SIMD_16_REG(x) ? cb1"%I"ca1: \
IS_SIMD_DATA_REG(x)? cb1"%D"ca1: \
IS_REG(x) ? cb1"%r"ca1: \
usesAuxReg ? cb"%a"ca : \
IS_SMALL(x) ? cb"%d"ca : cb"%h"ca))
#define WRITE_FORMAT_LB() strcat(formatString, "[")
#define WRITE_FORMAT_RB() strcat(formatString, "]")
#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT("nop");
#define NEXT_WORD(x) (offset += 4, state->words[x])
#define NEXT_WORD_AC(x) (offset += 2, state->words[x])
#define add_target(x) (state->targets[state->tcnt++] = (x))
static short int enable_simd = 0;
static short int enable_insn_stream = 0;
static const char *
core_reg_name(struct arcDisState *state, int val)
{
if (state->coreRegName)
return (*state->coreRegName)(state->_this, val);
return 0;
}
static const char *
aux_reg_name(struct arcDisState *state, int val)
{
if (state->auxRegName)
return (*state->auxRegName)(state->_this, val);
return 0;
}
static const char *
cond_code_name(struct arcDisState *state, int val)
{
if (state->condCodeName)
return (*state->condCodeName)(state->_this, val);
return 0;
}
static const char *
instruction_name(struct arcDisState *state, int op1, int op2, int *flags)
{
if (state->instName)
return (*state->instName)(state->_this, op1, op2, flags);
return 0;
}
static void
mwerror(struct arcDisState *state, const char *msg)
{
if (state->err != 0)
(*state->err)(state->_this, (msg));
}
static const char *
post_address(struct arcDisState *state, int addr)
{
static char id[3*_NELEM(state->addresses)];
unsigned int j, i = state->acnt;
if (i < _NELEM(state->addresses)) {
state->addresses[i] = addr;
++state->acnt;
j = i*3;
id[j+0] = '@';
id[j+1] = '0'+i;
id[j+2] = 0;
return id+j;
}
return "";
}
static void
my_sprintf (struct arcDisState *state, char *buf, const char*format, ...)
{
char *bp;
const char *p;
int size, leading_zero, regMap[2];
va_list ap;
va_start(ap,format);
bp = buf;
*bp = 0;
p = format;
regMap[0] = 0;
regMap[1] = 0;
while (1)
switch(*p++) {
case 0: goto DOCOMM; /*(return) */
default:
*bp++ = p[-1];
break;
case '%':
size = 0;
leading_zero = 0;
RETRY: ;
switch(*p++)
{
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
/* size. */
size = p[-1]-'0';
if (size == 0) leading_zero = 1; /* e.g. %08x */
while (*p >= '0' && *p <= '9')
size = size*10+*p-'0', p++;
goto RETRY;
}
#define inc_bp() bp = bp+strlen(bp)
case 'h':
{
unsigned u = va_arg(ap,int);
/*
* Hex. We can change the format to 0x%08x in
* one place, here, if we wish.
* We add underscores for easy reading.
*/
#define CDT_DEBUG
if (u > 65536)
#ifndef CDT_DEBUG
sprintf(bp,"0x%x_%04x",u >> 16, u & 0xffff);
#else
sprintf(bp,"0x%08x",u);
#endif // CDT_DEBUG
else
sprintf(bp,"0x%x",u);
inc_bp();
}
break;
case 'X': case 'x':
{
int val = va_arg(ap,int);
if (size != 0)
if (leading_zero) sprintf(bp,"%0*x",size,val);
else sprintf(bp,"%*x",size,val);
else sprintf(bp,"%x",val);
inc_bp();
}
break;
case 'd':
{
int val = va_arg(ap,int);
if (size != 0) sprintf(bp,"%*d",size,val);
else sprintf(bp,"%d",val);
inc_bp();
}
break;
case 'r':
{
/* Register. */
int val = va_arg(ap,int);
#define REG2NAME(num, name) case num: sprintf(bp,""name); \
regMap[(num<32)?0:1] |= 1<<(num-((num<32)?0:32)); break;
switch (val)
{
REG2NAME(26, "gp");
REG2NAME(27, "fp");
REG2NAME(28, "sp");
REG2NAME(29, "ilink1");
REG2NAME(30, "ilink2");
REG2NAME(31, "blink");
REG2NAME(60, "lp_count");
REG2NAME(63, "pcl");
default:
{
const char *ext;
ext = core_reg_name(state, val);
if (ext) sprintf(bp, "%s", ext);
else sprintf(bp,"r%d",val);
}break;
}
inc_bp();
} break;
case 'a':
{
/* Aux Register. */
int val = va_arg(ap,int);
char *ret;
ret = arc_aux_reg_name(val);
if(ret)
sprintf(bp,"%s",ret);
else
{
const char *ext;
ext = aux_reg_name(state, val);
if (ext) sprintf(bp, "%s", ext);
else my_sprintf(state, bp,"%h",val);
}
inc_bp();
}
break;
case 's':
{
sprintf(bp,"%s",va_arg(ap,char*));
inc_bp();
}
break;
case '*':
{
#if 0
va_arg(ap,char*);
inc_bp();
break;
#elif 1 /* used for prefetch to skip an argument. */
va_arg(ap,int);
break;
#else
extern void abort (void);
abort ();
#endif
}
/* SIMD operands follow*/
case 'S':
{
int val = va_arg (ap,int);
sprintf (bp, "vr%d",val);
inc_bp ();
break;
}
case 'I':
{
int val = va_arg (ap,int);
sprintf (bp, "i%d",val);
inc_bp ();
break;
}
case 'D':
{
int val = va_arg (ap,int);
sprintf (bp, "dr%d",val);
inc_bp ();
break;
}
/* SIMD operands end */
default:
fprintf(stderr,"?? format %c\n",p[-1]);
break;
}
}
DOCOMM:
*bp = 0;
va_end (ap);
}
static const char *condName[] =
{
/* 0..15. */
"" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
"nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz",
"ss" , "sc"
};
static void
write_instr_name_(struct arcDisState *state,
const char *instrName,
int cond,
int condCodeIsPartOfName,
int flag,
int signExtend,
int addrWriteBack,
int directMem)
{
if(!instrName)
return;
strncpy(state->instrBuffer, instrName, sizeof(state->instrBuffer)-1);
if (cond > 0)
{
int condlim = 0; /* condition code limit*/
const char *cc = 0;
if (!condCodeIsPartOfName) strcat(state->instrBuffer, ".");
condlim = 18;
if (cond < condlim)
cc = condName[cond];
else
cc = cond_code_name(state, cond);
if (!cc) cc = "???";
strcat(state->instrBuffer, cc);
}
if (flag) strcat(state->instrBuffer, ".f");
if (state->nullifyMode)
if (strstr(state->instrBuffer, ".d") == NULL)
strcat(state->instrBuffer, ".d");
if (signExtend) strcat(state->instrBuffer, ".x");
switch (addrWriteBack)
{
case 1: strcat(state->instrBuffer, ".a"); break;
case 2: strcat(state->instrBuffer, ".ab"); break;
case 3: strcat(state->instrBuffer, ".as"); break;
}
if (directMem) strcat(state->instrBuffer, ".di");
}
#define write_instr_name() {\
write_instr_name_(state, instrName,cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem); \
formatString[0] = '\0'; \
}
enum
{
op_BC = 0, op_BLC = 1, op_LD = 2, op_ST = 3, op_MAJOR_4 = 4,
/* START ARC LOCAL */
op_MAJOR_5 = 5, op_MAJOR_6 = 6, op_SIMD=9, op_LD_ADD = 12, op_ADD_SUB_SHIFT = 13,
/* END ARC LOCAL */
op_ADD_MOV_CMP = 14, op_S = 15, op_LD_S = 16, op_LDB_S = 17,
op_LDW_S = 18, op_LDWX_S = 19, op_ST_S = 20, op_STB_S = 21,
op_STW_S = 22, op_Su5 = 23, op_SP = 24, op_GP = 25, op_Pcl = 26,
op_MOV_S = 27, op_ADD_CMP = 28, op_BR_S = 29, op_B_S = 30, op_BL_S = 31
};
extern disassemble_info tm_print_insn_info;
/*
* bfd_getm32 - To retrieve the upper 16-bits of the ARCtangent-A5
* basecase (32-bit) instruction
*/
static bfd_vma
bfd_getm32 (data)
unsigned int data;
{
bfd_vma value = 0;
value = ((data & 0xff00) | (data & 0xff)) << 16;
value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
return value;
}
/*
* bfd_getm32_ac - To retrieve the upper 8-bits of the ARCompact
* 16-bit instruction
*/
static bfd_vma
bfd_getm32_ac (data)
unsigned int data;
{
bfd_vma value = 0;
value = ((data & 0xff) << 8 | (data & 0xff00) >> 8);
return value;
}
/*
* sign_extend - Sign Extend the value
*
*/
static int
sign_extend (int value, int bits)
{
if (BIT(value, (bits-1)))
value |= (0xffffffff << bits);
return value;
}
/* dsmOneArcInst - This module is used to identify the instruction
* and to decode them based on the ARCtangent-A5
* instruction set architecture.
* First, the major opcode is computed. Based on the
* major opcode and sub opcode, the instruction is
* identified. The appropriate decoding class is assigned
* based on the instruction.Further subopcode 2 is used in
* cases where decoding upto subopcode1 is not possible.
*
* The instruction is then decoded accordingly.
*/
static int
dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info)
{
int subopcode, mul;
int condCodeIsPartOfName=0;
int decodingClass;
const char *instrName;
int fieldAisReg=1, fieldBisReg=1, fieldCisReg=1;
int fieldA=0, fieldB=0, fieldC=0;
int flag=0, cond=0, is_shimm=0, is_limm=0;
int signExtend=0, addrWriteBack=0, directMem=0;
int is_linked=0;
int offset=0;
int usesAuxReg = 0;
int usesSimdRegA= 0, usesSimdRegB=0, usesSimdRegC=0,simd_scale_u8=-1;
int flags = !E_ARC_MACH_A4;
char formatString[60];
state->nullifyMode = BR_exec_when_no_jump;
state->isBranch = 0;
state->_mem_load = 0;
state->_ea_present = 0;
state->_load_len = 0;
state->ea_reg1 = no_reg;
state->ea_reg2 = no_reg;
state->_offset = 0;
state->sourceType = ARC_UNDEFINED;
/* ARCtangent-A5 basecase instruction and little-endian mode */
if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4))
state->words[0] = bfd_getm32(state->words[0]);
if (state->instructionLen == 4)
{
if (!NEXT_WORD(0))
return 0;
/* Get the major opcode of the ARCtangent-A5 32-bit instruction. */
state->_opcode = OPCODE(state->words[0]);
}
else
{
/* ARCompact 16-bit instruction */
if (!NEXT_WORD_AC(0))
return 0;
/* Get the major opcode of the ARCompact 16-bit instruction. */
state->_opcode = OPCODE_AC(state->words[0]);
}
instrName = 0;
decodingClass = 0; /* default! */
mul = 0;
condCodeIsPartOfName=0;
state->commNum = 0;
state->tcnt = 0;
state->acnt = 0;
state->flow = noflow;
/* Find the match for the opcode. Once the major opcode category is
* identified, get the subopcode to determine the exact instruction.
* Based on the instruction identified, select the decoding class.
* If condition code is part of the instruction name, then set the
* flag 'condCodeIsPartOfName'.
* For branch, jump instructions set 'isBranch' (state->isBranch).
*/
switch (state->_opcode)
{
case op_BC:
/* Branch Conditionally */
instrName = "b";
decodingClass = 13;
condCodeIsPartOfName = 1;
state->isBranch = 1;
break;
case op_BLC:
/* Branch and Link, Compare and Branch */
decodingClass = 9;
state->isBranch = 1;
switch (BITS(state->words[0],16,16))
{
case 0:
if (!instrName)
instrName = "bl";
decodingClass = 13;
condCodeIsPartOfName = 1;
break;
case 1:
switch (BITS(state->words[0],0,3))
{
case 0: instrName = "breq"; break;
case 1: instrName = "brne"; break;
case 2: instrName = "brlt"; break;
case 3: instrName = "brge"; break;
case 4: instrName = "brlo"; break;
case 5: instrName = "brhs"; break;
case 14: instrName = "bbit0"; break;
case 15: instrName = "bbit1"; break;
default:
instrName = "??? (0[3])";
state->flow = invalid_instr;
break;
}
break;
default:
instrName = "??? (0[3])";
state->flow = invalid_instr;
break;
}
break;
case op_LD:
/* Load register with offset [major opcode 2] */
decodingClass = 6;
switch (BITS(state->words[0],7,8))
{
case 0: instrName = "ld"; state->_load_len = 4; break;
case 1: instrName = "ldb"; state->_load_len = 1; break;
case 2: instrName = "ldw"; state->_load_len = 2; break;
default:
instrName = "??? (0[3])";
state->flow = invalid_instr;
break;
}
break;
case op_ST:
/* Store register with offset [major opcode 0x03] */
decodingClass = 7;
switch (BITS(state->words[0],1,2))
{
case 0: instrName = "st"; break;
case 1: instrName = "stb"; break;
case 2: instrName = "stw"; break;
default:
instrName = "??? (2[3])";
state->flow = invalid_instr;
break;
}
break;
case op_MAJOR_4:
/* ARC 32-bit basecase instructions with 3 Operands */
decodingClass = 0; /* Default for 3 operand instructions */
subopcode = BITS(state->words[0],16,21);
switch (subopcode)
{
case 0: instrName = "add"; break;
case 1: instrName = "adc"; break;
case 2: instrName = "sub"; break;
case 3: instrName = "sbc"; break;
case 4: instrName = "and"; break;
case 5: instrName = "or"; break;
case 6: instrName = "bic"; break;
case 7: instrName = "xor"; break;
case 8: instrName = "max"; break;
case 9: instrName = "min"; break;
case 10:
{
if(state->words[0] == 0x264a7000)
{
instrName = "nop";
decodingClass = 26;
}
else
{
instrName = "mov";
decodingClass = 12;
}
break;
}
case 11: instrName = "tst"; decodingClass = 2; break;
case 12: instrName = "cmp"; decodingClass = 2; break;
case 13: instrName = "rcmp"; decodingClass = 2; break;
case 14: instrName = "rsub"; break;
case 15: instrName = "bset"; break;
case 16: instrName = "bclr"; break;
case 17: instrName = "btst"; decodingClass = 2; break;
case 18: instrName = "bxor"; break;
case 19: instrName = "bmsk"; break;
case 20: instrName = "add1"; break;
case 21: instrName = "add2"; break;
case 22: instrName = "add3"; break;
case 23: instrName = "sub1"; break;
case 24: instrName = "sub2"; break;
case 25: instrName = "sub3"; break;
case 30: instrName = "mpyw"; break;
case 31: instrName = "mpyuw"; break;
case 32:
case 33:
instrName = "j";
case 34:
case 35:
if (!instrName) instrName = "jl";
decodingClass = 4;
condCodeIsPartOfName = 1;
state->isBranch = 1;
break;
case 40:
instrName = "lp";
decodingClass = 11;
condCodeIsPartOfName = 1;
state->isBranch = 1;
break;
case 41: instrName = "flag"; decodingClass = 3; break;
case 42: instrName = "lr"; decodingClass = 10; break;
case 43: instrName = "sr"; decodingClass = 8; break;
case 47:
decodingClass = 1;
switch (BITS(state->words[0],0,5)) /* Checking based on Subopcode2 */
{
case 0: instrName = "asl"; break;
case 1: instrName = "asr"; break;
case 2: instrName = "lsr"; break;
case 3: instrName = "ror"; break;
case 4: instrName = "rrc"; break;
case 5: instrName = "sexb"; break;
case 6: instrName = "sexw"; break;
case 7: instrName = "extb"; break;
case 8: instrName = "extw"; break;
case 9: instrName = "abs"; break;
case 10: instrName = "not"; break;
case 11: instrName = "rlc"; break;
case 12: instrName = "ex";
decodingClass = 34;
break; // ramana adds
/* START ARC LOCAL */
case 16: instrName = "llock"; decodingClass = 34; break;
case 17: instrName = "scond"; decodingClass = 34; break;
/* END ARC LOCAL */
case 63:
decodingClass = 26;
switch (BITS(state->words[0],24,26))
{
case 1 : instrName = "sleep"; decodingClass = 32; break;
case 2 :
if((info->mach) == ARC_MACH_ARC7)
instrName = "trap0";
else
instrName = "swi";
break;
case 3:
if(BITS(state->words[0],22,23) == 1)
instrName = "sync" ;
break;
case 4 : instrName = "rtie" ; break;
case 5 : instrName = "brk"; break;
default:
instrName = "???";
state->flow=invalid_instr;
break;
}
break;
}
break;
}
if (!instrName)
{
subopcode = BITS(state->words[0],17,21);
decodingClass = 5;
switch (subopcode)
{
case 24: instrName = "ld"; state->_load_len = 4; break;
case 25: instrName = "ldb"; state->_load_len = 1; break;
case 26: instrName = "ldw"; state->_load_len = 2; break;
default:
instrName = "??? (0[3])";
state->flow = invalid_instr;
break;
}
}
break;
case op_MAJOR_5:
/* ARC 32-bit extension instructions */
decodingClass = 0; /* Default for Major opcode 5 ... */
subopcode = BITS(state->words[0],16,21);
switch (subopcode)
{
case 0: instrName = "asl"; break;
case 1: instrName = "lsr"; break;
case 2: instrName = "asr"; break;
case 3: instrName = "ror"; break;
case 4: instrName = "mul64"; mul =1; decodingClass = 2; break;
case 5: instrName = "mulu64"; mul =1; decodingClass = 2; break;
/* ARC A700 */
case 6: instrName = "adds" ;break;
case 7: instrName = "subs"; break;
case 8: instrName = "divaw"; break;
case 0xA: instrName = "asls"; break;
case 0xB: instrName = "asrs"; break;
case 0x28: instrName = "addsdw";break;
case 0x29: instrName = "subsdw"; break;
case 47:
switch(BITS(state->words[0],0,5))
{
case 0: instrName = "swap"; decodingClass = 1; break;
case 1: instrName = "norm"; decodingClass = 1; break;
/* ARC A700 DSP Extensions */
case 2: instrName = "sat16"; decodingClass = 1; break;
case 3: instrName = "rnd16"; decodingClass = 1; break;
case 4: instrName = "abssw"; decodingClass = 1; break;
case 5: instrName = "abss"; decodingClass = 1; break;
case 6: instrName = "negsw"; decodingClass = 1; break;
case 7: instrName = "negs"; decodingClass = 1; break;
case 8: instrName = "normw"; decodingClass = 1; break;
/* START ARC LOCAL */
case 9: instrName = "swape"; decodingClass = 1; break;
/* END ARC LOCAL */
default:
instrName = "???";
state->flow =invalid_instr;
break;
}
break;
default:
instrName = "??? (2[3])";
state->flow = invalid_instr;
break;
}
break;
/* START ARC LOCAL */
case op_MAJOR_6:
decodingClass = 44; /* Default for Major opcode 6 ... */
subopcode = BITS(state->words[0],0,5);
switch (subopcode)
{
case 26: /* 0x1a */ instrName = "rtsc"; break;
default:
instrName = "??? (2[3])";
state->flow = invalid_instr;
break;
}
break;
/* END ARC LOCAL */
/* Aurora SIMD instruction support*/
case op_SIMD: