{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":223218149,"defaultBranch":"main","name":"mempool","ownerLogin":"pulp-platform","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2019-11-21T16:34:37.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/14332106?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1717156858.0","currentOid":""},"activityList":{"items":[{"before":"0e9197718ba3e00c863d5c8627732364e5ce966b","after":"7c2a3110837f5a86424b3e432a026c74f9e5917f","ref":"refs/heads/doc","pushedAt":"2024-06-04T08:01:58.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[TeraPool] The TeraPool Project Report Revision, adding table for IPU and FPU instructions support and typos correction","shortMessageHtmlLink":"[TeraPool] The TeraPool Project Report Revision, adding table for IPU…"}},{"before":"e74fcbe1a26ed223d1e3d906c0022411e855fbc2","after":"905997645cc0762312c9d7c74357705a29b66452","ref":"refs/heads/terapool_noc","pushedAt":"2024-06-03T21:31:59.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Aquaticfuller","name":"zexinfu","path":"/Aquaticfuller","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/59481680?s=80&v=4"},"commit":{"message":"[RTL] Connect the mempool group to the floonoc chimney","shortMessageHtmlLink":"[RTL] Connect the mempool group to the floonoc chimney"}},{"before":"bc2a257bdcc0a7289e0680c697dd63ed82e178af","after":"e74fcbe1a26ed223d1e3d906c0022411e855fbc2","ref":"refs/heads/terapool_noc","pushedAt":"2024-06-03T15:36:01.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[RTL] Draft to connect with chimeny","shortMessageHtmlLink":"[RTL] Draft to connect with chimeny"}},{"before":"b5044d8d0d14af1b01792369ad197ed87eb29d7c","after":"7fb0bb9ec61d27728a66607ad50d2be077409684","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-06-03T07:49:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[LLVM] Change llvm to github version.","shortMessageHtmlLink":"[LLVM] Change llvm to github version."}},{"before":"71bcb6f604f0b70250d58ab4f19d21856a658c81","after":"bc2a257bdcc0a7289e0680c697dd63ed82e178af","ref":"refs/heads/terapool_noc","pushedAt":"2024-05-31T14:35:55.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[Tile] Change tile level remote access interface, round robin within each of ports when access remote group","shortMessageHtmlLink":"[Tile] Change tile level remote access interface, round robin within …"}},{"before":null,"after":"71bcb6f604f0b70250d58ab4f19d21856a658c81","ref":"refs/heads/terapool_noc","pushedAt":"2024-05-31T12:00:58.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[Bender] Change Bender version to workaround the VCS bug","shortMessageHtmlLink":"[Bender] Change Bender version to workaround the VCS bug"}},{"before":"d3f2e016100a041b776bc41f5ed3b5d48104899e","after":"b5044d8d0d14af1b01792369ad197ed87eb29d7c","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-31T09:22:07.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"Rebase onto latest main.","shortMessageHtmlLink":"Rebase onto latest main."}},{"before":"de753b89082049eeb67563e8582e0d30ddd92711","after":"d3f2e016100a041b776bc41f5ed3b5d48104899e","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-30T15:09:41.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[MemPool-Spatz][TCDM Burst]\nAdd functionalities of TCDM Burst and grouped responses.\n\n[MemPool-Spatz][Burst]\nWIP: clean spatz benchmarks.\n\n[TCDM Burst]\n1. Fix local visits by not sending burst requests.\n2. Clean up code.\n3. Disable FP8 and INT8 for Spatz by default.\n4. Reduce FIFO/ROB depth back to 8 except Spatz VLSU.\n\n[MemPool-Spatz]\nPoint to latest Spatz.\n\n[TCDM Burst]\n1. Change the parameters to control using burst, grouped rsp and parallel burst manager.\n2. Change the ROB instantiation in Spatz VLSU.\n\n[TCDM Burst] Bug Fix\n1. Fix the DMA bug.\n2. Fix a bug related to tcdm_burst_pkg setting.\n3. Update kernels for Spatz.\n\n[TCDM Burst][Bug Fix]\nFix a problem of assigning a one-bit signal to a two-bit signal.\n\n[TCDM Burst]\nClean code.\n\nClean Code\n1. Bump Spatz to lastest version\n2. Add block names and add waveforms for burst_manager\n3. Initialize response for write to 0 in data_group to eliminate x\n4. Only generate one `burst_cutter` module since it is all we need\n\n[WIP] Clean code for vector burst related blocks.\n\n[WIP] Clean Code\n1. Clean the unused configuration files.\n2. Update Spatz to latest version.\n3. Fix the axpy kernel.\n4. Let fft kernel check results by default.\n\nCode Clean: Fix whitespaces in README.","shortMessageHtmlLink":"[MemPool-Spatz][TCDM Burst]"}},{"before":"4c9cdcbba8cadcd9218731b39d8e043ad350de8d","after":"de753b89082049eeb67563e8582e0d30ddd92711","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-30T14:26:04.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[WIP] Clean Code\n1. Clean the unused configuration files.\n2. Update Spatz to latest version.\n3. Fix the axpy kernel.\n4. Let fft kernel check results by default.","shortMessageHtmlLink":"[WIP] Clean Code"}},{"before":"bb8af112752019393a5bb13581f2dc90fb485909","after":"0e9197718ba3e00c863d5c8627732364e5ce966b","ref":"refs/heads/doc","pushedAt":"2024-05-29T09:27:14.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[cachepool] Add cachepool folder for document archiev","shortMessageHtmlLink":"[cachepool] Add cachepool folder for document archiev"}},{"before":"39ba275949e93c6f7b1c2465c6982f049de3beea","after":"4c9cdcbba8cadcd9218731b39d8e043ad350de8d","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-24T15:45:00.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[WIP] Clean code for vector burst related blocks.","shortMessageHtmlLink":"[WIP] Clean code for vector burst related blocks."}},{"before":"6d8533980987adfc2e12e233fc5f35d92686503a","after":"39ba275949e93c6f7b1c2465c6982f049de3beea","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-24T09:40:23.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"Clean Code\n1. Bump Spatz to lastest version\n2. Add block names and add waveforms for burst_manager\n3. Initialize response for write to 0 in data_group to eliminate x\n4. Only generate one `burst_cutter` module since it is all we need","shortMessageHtmlLink":"Clean Code"}},{"before":"0b0f888a4f775a15067a60f5cfff22662d52088b","after":"bb8af112752019393a5bb13581f2dc90fb485909","ref":"refs/heads/doc","pushedAt":"2024-05-21T14:36:33.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[README] Correct the line breaking","shortMessageHtmlLink":"[README] Correct the line breaking"}},{"before":"39b70d70a23d51568708d7f61ec1f77e4c4eb29a","after":"0b0f888a4f775a15067a60f5cfff22662d52088b","ref":"refs/heads/doc","pushedAt":"2024-05-21T14:28:41.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[TeraPool] Add TeraPool project report","shortMessageHtmlLink":"[TeraPool] Add TeraPool project report"}},{"before":"53972f23b99996bf461fa2fd11942deaa6c336d5","after":"39b70d70a23d51568708d7f61ec1f77e4c4eb29a","ref":"refs/heads/doc","pushedAt":"2024-05-21T14:22:31.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[repo] remove gitlab-ci and gitmodules, update README with typo fixes","shortMessageHtmlLink":"[repo] remove gitlab-ci and gitmodules, update README with typo fixes"}},{"before":"9ff0d004969ecdd220c28630a5b6e64941ddaacd","after":"53972f23b99996bf461fa2fd11942deaa6c336d5","ref":"refs/heads/doc","pushedAt":"2024-05-21T14:19:07.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[repo] Structure the repo and update README","shortMessageHtmlLink":"[repo] Structure the repo and update README"}},{"before":"065efa9bdd6b3224972f26f2cb1bbb7c193bfe28","after":null,"ref":"refs/heads/zexin/mempool-spatz-tiling","pushedAt":"2024-05-08T19:24:16.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"Aquaticfuller","name":"zexinfu","path":"/Aquaticfuller","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/59481680?s=80&v=4"}},{"before":null,"after":"065efa9bdd6b3224972f26f2cb1bbb7c193bfe28","ref":"refs/heads/zexin/mempool-spatz-tiling","pushedAt":"2024-05-08T14:13:21.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Aquaticfuller","name":"zexinfu","path":"/Aquaticfuller","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/59481680?s=80&v=4"},"commit":{"message":"[MemPool-Spatz] Fix git submodule of Spatz.","shortMessageHtmlLink":"[MemPool-Spatz] Fix git submodule of Spatz."}},{"before":"9dd79afac4557e28018e9b7187913343321690ca","after":null,"ref":"refs/heads/zexin/mempool-spatz-tiling","pushedAt":"2024-05-08T14:13:08.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"Aquaticfuller","name":"zexinfu","path":"/Aquaticfuller","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/59481680?s=80&v=4"}},{"before":null,"after":"9dd79afac4557e28018e9b7187913343321690ca","ref":"refs/heads/zexin/mempool-spatz-tiling","pushedAt":"2024-05-08T14:13:03.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Aquaticfuller","name":"zexinfu","path":"/Aquaticfuller","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/59481680?s=80&v=4"},"commit":{"message":"[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system (#106)\n\n* [TeraPool] Configurations Changes for TeraPool merge into MemPool\r\n\r\n* [DRAMsys] add dram rtl model\r\n\r\n* [DRAMsys] fix simulation bug\r\n\r\n* [DRAMsys] setting to add dramsys support\r\n\r\n* [DRAMsys] fix bugs: stack overflow when reading from dramsys\r\n\r\n* [Software] Temp change for easy debug\r\n\r\n* [DMA] DMA bug fix and mempool trace bug fix\r\n\r\n* [DRAM] Update DRAM lib with AXI reordering\r\n\r\n* [DRAM] Format codes\r\n\r\n* [DRAM] Merge SRAM and DRAM simulation in one RTL file\r\n\r\n* [Software] Update memcpy kernel\r\n\r\n* [Makefile] Update Makefile control simulation with dram var\r\n\r\n* [DRAM] Delete old file\r\n\r\n* [Bender] Remove the deleted RTL file\r\n\r\n* [RTL] Change the AXI MUX to AXI Xbar to connect the DRAM\r\n\r\n* [DRAM] DRAM update to support interleaved address mapping\r\n\r\n* [DRAM] Update DRAM model to support interleaved mode and fix write bugs\r\n\r\n* [Hardware] Support the different interleave mode for DRAM access\r\n\r\n* [Config] L2 address and size update\r\n\r\n* [Kernel] memcpy kernel update\r\n\r\n* [DRAM] Non-Ideal PHY latency support\r\n\r\n* [DRAM] Python Script for DRAM Bandwidth Analysis\r\n\r\n* [Format] Format the files for CI check\r\n\r\n* [Format] Format and put liscenses to files for CI checking\r\n\r\n* [Format] Format DRAM python script for CI check\r\n\r\n* [AXI] Update Auto Spliter Adding, Update Interleave SystemVerilog Writing Style\r\n\r\n* [HBM2E] Update DRAM HBM model to MICRON HBM2E-3600\r\n\r\n* [Env] Update some configurations, include the fifo size and DRAM configuration\r\n\r\n* [Rebase] Rebase the DRAM work on top of main branch\r\n\r\n* [Config] Complete MinPool config for CI checking\r\n\r\n* [memcpy] Reduce transfer size for MinPool CI check\r\n\r\n* [memcpy] Reduce transfer size for MinPool CI check\r\n\r\n* [memcpy] Remove unused dump from kernel\r\n\r\n* [FIFO depth] The Fifo depth tune for support 8 outstanding transctions to hide DRAM latency\r\n\r\n* [DRAMsys] Remove the local version of DRAMsys hardware folder, add the open-sourced DRAMsys as a submodule\r\n\r\n* [Config] Move the dram related configurations to the config.mk\r\n\r\n* [Makefile] Modify Makefile for updating submodule, patching dram configurations, and compiling dramsys dynamic library.\r\n\r\n* [hardware] hardware change for the new version dramsys support\r\n\r\n* [DRAM] Add the configuration files for HBM2 DRAM simulation, these file will patch to dram_sim_rtl submodule by  makefile target\r\n\r\n* [tb] Change back the simulation clk period to 2ns, but 1ns will have better DRAM BW as the HBM2 support upto 3600Gbps DDR\r\n\r\n* [Bender] Update bender to the correct RTL name, as DRAMsys updated themself\r\n\r\n* [software] Update memcpy kernel with reasonable transfer size and turn on the verification\r\n\r\n* [config] Change simulation to SRAM as L2 for CI checking\r\n\r\n* [CI test] Fix tb whitespace tailing and change the bender to compile dramsys rtl only by vsim\r\n\r\n* [CHANGELOG and README] Add changelog and readme for DRAM co-simulation\r\n\r\n* [Compiler version] Remove the cmake and gcc version from Makefile and update the ci.yml\r\n\r\n* [rtl] As we solved the bug in DRAM reset, set the reset edge back to the original version\r\n\r\n* Change the memcpy result dump CSR and remove the repeat in Makefile\r\n\r\n---------\r\n\r\nCo-authored-by: Zhang Chi <chizhang@iis.ee.ethz.ch>","shortMessageHtmlLink":"[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2202122436\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pulp-platform/mempool/issues/106\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pulp-platform/mempool/pull/106/hovercard\" href=\"https://github.com/pulp-platform/mempool/pull/106\">#106</a>)"}},{"before":"22f063e623fd70dcbb43e28aa5c8708371507903","after":"6d8533980987adfc2e12e233fc5f35d92686503a","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-05-08T13:33:44.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[TCDM Burst]\nClean code.","shortMessageHtmlLink":"[TCDM Burst]"}},{"before":"63b3b25ed906b9546455196d6b80b0e2340c1f53","after":null,"ref":"refs/heads/terapool_DRAM_RTL","pushedAt":"2024-05-06T11:49:38.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"}},{"before":"149954574fbc0c444612b6ecaedbb121534fb579","after":"9dd79afac4557e28018e9b7187913343321690ca","ref":"refs/heads/main","pushedAt":"2024-05-06T11:49:37.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system (#106)\n\n* [TeraPool] Configurations Changes for TeraPool merge into MemPool\r\n\r\n* [DRAMsys] add dram rtl model\r\n\r\n* [DRAMsys] fix simulation bug\r\n\r\n* [DRAMsys] setting to add dramsys support\r\n\r\n* [DRAMsys] fix bugs: stack overflow when reading from dramsys\r\n\r\n* [Software] Temp change for easy debug\r\n\r\n* [DMA] DMA bug fix and mempool trace bug fix\r\n\r\n* [DRAM] Update DRAM lib with AXI reordering\r\n\r\n* [DRAM] Format codes\r\n\r\n* [DRAM] Merge SRAM and DRAM simulation in one RTL file\r\n\r\n* [Software] Update memcpy kernel\r\n\r\n* [Makefile] Update Makefile control simulation with dram var\r\n\r\n* [DRAM] Delete old file\r\n\r\n* [Bender] Remove the deleted RTL file\r\n\r\n* [RTL] Change the AXI MUX to AXI Xbar to connect the DRAM\r\n\r\n* [DRAM] DRAM update to support interleaved address mapping\r\n\r\n* [DRAM] Update DRAM model to support interleaved mode and fix write bugs\r\n\r\n* [Hardware] Support the different interleave mode for DRAM access\r\n\r\n* [Config] L2 address and size update\r\n\r\n* [Kernel] memcpy kernel update\r\n\r\n* [DRAM] Non-Ideal PHY latency support\r\n\r\n* [DRAM] Python Script for DRAM Bandwidth Analysis\r\n\r\n* [Format] Format the files for CI check\r\n\r\n* [Format] Format and put liscenses to files for CI checking\r\n\r\n* [Format] Format DRAM python script for CI check\r\n\r\n* [AXI] Update Auto Spliter Adding, Update Interleave SystemVerilog Writing Style\r\n\r\n* [HBM2E] Update DRAM HBM model to MICRON HBM2E-3600\r\n\r\n* [Env] Update some configurations, include the fifo size and DRAM configuration\r\n\r\n* [Rebase] Rebase the DRAM work on top of main branch\r\n\r\n* [Config] Complete MinPool config for CI checking\r\n\r\n* [memcpy] Reduce transfer size for MinPool CI check\r\n\r\n* [memcpy] Reduce transfer size for MinPool CI check\r\n\r\n* [memcpy] Remove unused dump from kernel\r\n\r\n* [FIFO depth] The Fifo depth tune for support 8 outstanding transctions to hide DRAM latency\r\n\r\n* [DRAMsys] Remove the local version of DRAMsys hardware folder, add the open-sourced DRAMsys as a submodule\r\n\r\n* [Config] Move the dram related configurations to the config.mk\r\n\r\n* [Makefile] Modify Makefile for updating submodule, patching dram configurations, and compiling dramsys dynamic library.\r\n\r\n* [hardware] hardware change for the new version dramsys support\r\n\r\n* [DRAM] Add the configuration files for HBM2 DRAM simulation, these file will patch to dram_sim_rtl submodule by  makefile target\r\n\r\n* [tb] Change back the simulation clk period to 2ns, but 1ns will have better DRAM BW as the HBM2 support upto 3600Gbps DDR\r\n\r\n* [Bender] Update bender to the correct RTL name, as DRAMsys updated themself\r\n\r\n* [software] Update memcpy kernel with reasonable transfer size and turn on the verification\r\n\r\n* [config] Change simulation to SRAM as L2 for CI checking\r\n\r\n* [CI test] Fix tb whitespace tailing and change the bender to compile dramsys rtl only by vsim\r\n\r\n* [CHANGELOG and README] Add changelog and readme for DRAM co-simulation\r\n\r\n* [Compiler version] Remove the cmake and gcc version from Makefile and update the ci.yml\r\n\r\n* [rtl] As we solved the bug in DRAM reset, set the reset edge back to the original version\r\n\r\n* Change the memcpy result dump CSR and remove the repeat in Makefile\r\n\r\n---------\r\n\r\nCo-authored-by: Zhang Chi <chizhang@iis.ee.ethz.ch>","shortMessageHtmlLink":"[DRAMsys 5.0] DRAMsys co-simulation with MemPool/TeraPool system (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2202122436\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pulp-platform/mempool/issues/106\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pulp-platform/mempool/pull/106/hovercard\" href=\"https://github.com/pulp-platform/mempool/pull/106\">#106</a>)"}},{"before":"d4b06f21831cc549f7ae9f4bc1277e8029cef60c","after":"63b3b25ed906b9546455196d6b80b0e2340c1f53","ref":"refs/heads/terapool_DRAM_RTL","pushedAt":"2024-05-03T11:04:56.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"Change the memcpy result dump CSR and remove the repeat in Makefile","shortMessageHtmlLink":"Change the memcpy result dump CSR and remove the repeat in Makefile"}},{"before":"92891f6829fda7d8c6f2bfd0329fe47be5c278ae","after":"d4b06f21831cc549f7ae9f4bc1277e8029cef60c","ref":"refs/heads/terapool_DRAM_RTL","pushedAt":"2024-05-02T17:05:13.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[rtl] As we solved the bug in DRAM reset, set the reset edge back to the original version","shortMessageHtmlLink":"[rtl] As we solved the bug in DRAM reset, set the reset edge back to …"}},{"before":"6ab46ef9ec7b5b3482dc41de6dfc98d6fc936162","after":"92891f6829fda7d8c6f2bfd0329fe47be5c278ae","ref":"refs/heads/terapool_DRAM_RTL","pushedAt":"2024-05-02T16:53:32.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[Compiler version] Remove the cmake and gcc version from Makefile and update the ci.yml","shortMessageHtmlLink":"[Compiler version] Remove the cmake and gcc version from Makefile and…"}},{"before":"2d19b34daeeb2f9f3ed3c48cc13e25d501752adb","after":"6ab46ef9ec7b5b3482dc41de6dfc98d6fc936162","ref":"refs/heads/terapool_DRAM_RTL","pushedAt":"2024-05-02T16:48:28.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"yichao-zh","name":"Yichao Zhang","path":"/yichao-zh","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78019111?s=80&v=4"},"commit":{"message":"[Format] solve the last line format","shortMessageHtmlLink":"[Format] solve the last line format"}},{"before":"5c48e30c2d538c48b6281347551493de4ca9201a","after":"149954574fbc0c444612b6ecaedbb121534fb579","ref":"refs/heads/main","pushedAt":"2024-04-29T11:06:56.000Z","pushType":"pr_merge","commitsCount":64,"pusher":{"login":"mbertuletti","name":"Marco Bertuletti","path":"/mbertuletti","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/101246366?s=80&v=4"},"commit":{"message":"Merge pull request #98 from pulp-platform/mbertuletti/mempool_fpu\n\nMemPool FPU","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2184506980\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pulp-platform/mempool/issues/98\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pulp-platform/mempool/pull/98/hovercard\" href=\"https://github.com/pulp-platform/mempool/pull/98\">#98</a> from pulp-platform/mbertuletti/mempool_fpu"}},{"before":"7c417422b2da826870376dbbc99be72544a8010d","after":null,"ref":"refs/heads/mbertuletti/mempool_fpu","pushedAt":"2024-04-29T11:06:56.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"mbertuletti","name":"Marco Bertuletti","path":"/mbertuletti","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/101246366?s=80&v=4"}},{"before":"38f2b71b5cebe1dc0542d0dc16aa795b4cf699ee","after":"22f063e623fd70dcbb43e28aa5c8708371507903","ref":"refs/heads/Diyou/tcdm-burst","pushedAt":"2024-04-28T09:56:38.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"DiyouS","name":"Diyou Shen","path":"/DiyouS","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99251048?s=80&v=4"},"commit":{"message":"[TCDM Burst] Bug Fix\n1. Fix the DMA bug.\n2. Fix a bug related to tcdm_burst_pkg setting.\n3. Update kernels for Spatz.","shortMessageHtmlLink":"[TCDM Burst] Bug Fix"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEW791IQA","startCursor":null,"endCursor":null}},"title":"Activity · pulp-platform/mempool"}