racing-the-beam

Racing the Beam

This folder accompanies the Project F blog post: Racing the Beam. These SystemVerilog designs race the beam to create simple demos. You can freely build on these MIT licensed designs. Have fun.

File layout:

• ice40 - designs for iCEBreaker and other Lattice iCE40 boards
• sim - simulation with Verilator and LibSDL; see the Simulation README
• xc7 - designs for Arty and other Xilinx 7 Series boards with VGA output
• xc7-dvi - designs for Nexys Video and other Xilinx 7 Series boards with DVI output

These designs make use of modules from the Project F library.

Demos

• Raster Bars
• Hitomezashi
• Hello
• Colour Cycle
• Bounce

Learn more about the designs and demos from Racing the Beam, or read on for build instructions.

Raster Bars running as a Verilator simulation.

iCEBreaker Build

You can build projects for iCEBreaker using the included Makefile with Yosys, nextpnr, and IceStorm Tools.

You can get pre-built binaries for Linux, Mac, and Windows from YosysHQ.

For example, to build rasterbars; clone the projf-explore git repo, then:

cd projf-explore/graphics/racing-the-beam/ice40
make rasterbars

After the build completes, you'll have a bin file, such as rasterbars.bin. Use the bin file to program your board:

iceprog rasterbars.bin

If you get the error Can't find iCE FTDI USB device, try running iceprog with sudo.

Tested Versions

The iCE40 designs have been tested with:

• OSS CAD Suite 2023-03-01

Arty Build

To create a Vivado project for the Digilent Artyå (original or A7-35T); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/graphics/racing-the-beam/xc7/vivado
source ./create_project.tcl

You can then build the designs as you would for any Vivado project.

Tested Versions

The Arty designs have been tested with:

• Vivado 2022.2

Other Xilinx 7 Series Boards

It's straightforward to adapt the project for other Xilinx 7 Series boards:

1. Create a suitable constraints file named <board>.xdc within the xc7 directory
2. Make a note of your board's FPGA part, such as xc7a35ticsg324-1L
3. Set the board and part names in Tcl, then source the create project script:

set board_name <board>
set fpga_part <fpga-part>
cd projf-explore/graphics/racing-the-beam/xc7/vivado
source ./create_project.tcl

Replace <board> and <fpga-part> with the actual board and part names.

Nexys Video Build

To create a Vivado project for the Digilent Nexys Video; clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/graphics/racing-the-beam/xc7-dvi/vivado
source ./create_project.tcl

You can then build the designs as you would for any Vivado project.

Tested Versions

The Nexys Video designs have been tested with:

• Vivado 2022.2

Verilator SDL Simulation

You can simulate these designs on your computer using Verilator and SDL. The Simulation README has build instructions.

Linting

If you have Verilator installed, you can run the linting shell script lint.sh to check the designs. Learn more from Verilog Lint with Verilator.

SystemVerilog?

These designs use a little SystemVerilog to make Verilog more pleasant. See the Library README for details of SV features used.