Simulation testbench for usb-to-uart coding

[buttercutter]

I have issue with simulating usb-to-uart coding using iverilog.
Please see below the output logs where vvp is forever stopped at simulation time step 0.

[phung@archlinux usb]$ iverilog -o usb_tb usb_uart.v usb_tb.v
usb_tb.v:29: warning: output port rx_data is coerced to inout.
usb_tb.v:30: warning: output port rx_strobe is coerced to inout.
[phung@archlinux usb]$ vvp usb_tb
VCD info: dumpfile usb_tb.vcd opened for output.
^C** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 0 ticks.
> finish
** Continue **
[phung@archlinux usb]$ 

To reproduce the exact issue that I am having now, please find attached the zip file containing all the modified design files + simulation testbench. I have also included cells_sim.v which takes care of SB_IO module for ice40 device.

usb_tb.v : simulation testbench

`timescale 1ns / 1ps

module usb_tb();

reg clk, clk_48mhz;
reg reset;

wire pin_usbp, pin_usbn;
wire pin_pu;

wire [7:0] rx_data;
wire rx_strobe;
reg [7:0] tx_data;
reg tx_strobe;

assign pin_usbp = pin_pu ?  tx_strobe :  rx_strobe;
assign pin_usbn = pin_pu ? ~tx_strobe : ~rx_strobe;

usb_uart dut
(
	.clk(clk),
	.clk_48mhz(clk_48mhz),
	.reset(reset),
	
	.pin_usbp(pin_usbp),
	.pin_usbn(pin_usbn),
	.pin_pu(pin_pu),
	
	.rx_data(rx_data),
	.rx_strobe(rx_strobe),
	.tx_data(tx_data),
	.tx_strobe(tx_strobe)
);

initial begin
 	$dumpfile("usb_tb.vcd"); 
 	$dumpvars; 
end 

initial
begin
	clk = 0;
	clk_48mhz = 0;
	reset = 0;
	tx_data = 0;
	tx_strobe = 0;

	@(posedge clk_48mhz);
	reset = 1;

	@(posedge clk_48mhz);
	@(posedge clk_48mhz);

	reset = 0;
		
	@(posedge clk_48mhz);
	tx_strobe = 1;
	tx_data = 1;
	
	@(posedge clk_48mhz);
	tx_data = 2;
	
	@(posedge clk_48mhz);
	tx_data = 3;
	
	#50 $finish;
end

always #5  clk = !clk; 
always #10  clk_48mhz = !clk_48mhz; 

endmodule

[phung@archlinux usb]$ git status --short
 M usb_serial_ep.v
 M usb_uart.v
 M ../util.v
?? ../icesugar.pcf
?? build.sh
?? usb_tb
?? usb_tb.v
?? usb_tb.vcd
[phung@archlinux usb]$ git diff usb_serial_ep.v
diff --git a/usb/usb_serial_ep.v b/usb/usb_serial_ep.v
index e90d817..b813028 100644
--- a/usb/usb_serial_ep.v
+++ b/usb/usb_serial_ep.v
@@ -23,7 +23,7 @@ module usb_serial_ep (
   input in_ep_grant,
   input in_ep_data_free,
   output reg in_ep_data_put = 0,
-  output [7:0] in_ep_data,
+  output reg [7:0] in_ep_data,^M
   output reg in_ep_data_done = 0,
   output in_ep_stall,
   input in_ep_acked,
@@ -37,7 +37,7 @@ module usb_serial_ep (
   input uart_tx_strobe,
 
   output [7:0] uart_rx_data,
-  output uart_rx_strobe
+  output reg uart_rx_strobe^M
 );
   // never stall the USB
   // todo: allow backpressure to stall the serial link
[phung@archlinux usb]$ git diff usb_uart.v 
diff --git a/usb/usb_uart.v b/usb/usb_uart.v
index 2ec7c31..d641a94 100644
--- a/usb/usb_uart.v
+++ b/usb/usb_uart.v
@@ -3,6 +3,7 @@
 
 `include "usb_serial.v"
 `include "../util.v"
+`include "/usr/share/yosys/ice40/cells_sim.v"^M
 
 module usb_uart (
   input  clk,
[phung@archlinux usb]$ git diff ../util.v 
diff --git a/util.v b/util.v
index 6c55b8d..910cab2 100644
--- a/util.v
+++ b/util.v
@@ -22,7 +22,7 @@
    x <= 32768   ? 15 : \
    x <= 65536   ? 16 : \
    -1
-
+/*
 function [7:0] hexdigit;
        input [3:0] x;
        begin
@@ -46,7 +46,7 @@ function [7:0] hexdigit;
                        "?";
        end
 endfunction
-
+*/
 module divide_by_n(
        input clk,
        input reset,
@@ -112,7 +112,7 @@ endmodule
 module pwm(
        input clk,
        input [BITS-1:0] bright,
-       output out
+       output reg out
 );
        parameter BITS = 8;
 
[phung@archlinux usb]$ 

[buttercutter]

One other issue is critical path slack violation inside usb_fs_rx.v module
Try to run ./build.sh inside the usb directory

Note: 1/42.36MHz = 8.5ns + 15.1ns = 23.6ns

ERROR: Max frequency for clock    'clk_48mhz': 42.36 MHz (FAIL at 48.00 MHz)

Info: Critical path report for clock 'clk_48mhz' (posedge -> posedge):
Info: curr total
Info:  1.4  1.4  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.bit_phase_SB_DFFSR_Q_D_SB_LUT4_O_LC.O
Info:  1.8  3.2    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.bit_phase[1] budget 0.509000 ns (11,3) -> (11,4)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.line_state_valid_SB_LUT4_O_LC.I2
Info:  1.2  4.4  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.line_state_valid_SB_LUT4_O_LC.O
Info:  3.1  7.4    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.line_state_valid budget 1.075000 ns (11,4) -> (11,9)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.I1
Info:  1.2  8.6  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.O
Info:  1.8 10.4    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3_SB_LUT4_O_I3 budget 0.013000 ns (11,9) -> (10,10)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3_SB_LUT4_O_LC.I3
Info:  0.9 11.3  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3_SB_LUT4_O_LC.O
Info:  1.8 13.0    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I2_I3 budget 0.009000 ns (10,10) -> (11,11)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I3_LC.I2
Info:  1.2 14.2  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I3_LC.O
Info:  1.8 16.0    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.pid_complete_SB_LUT4_I3_O budget -0.390000 ns (11,11) -> (12,12)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_LC.I3
Info:  0.9 16.9  Source serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_LC.O
Info:  4.3 21.2    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_O budget 1.708000 ns (12,12) -> (13,31)
Info:                Sink $gbuf_serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_O_$glb_ce.USER_SIGNAL_TO_GLOBAL_BUFFER
Info:  1.6 22.8  Source $gbuf_serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_O_$glb_ce.GLOBAL_BUFFER_OUTPUT
Info:  0.7 23.5    Net serial.usb_fs_pe_inst.usb_fs_rx_inst.next_packet_valid_SB_LUT4_I3_O_SB_LUT4_I2_1_O_$glb_ce budget 1.707000 ns (13,31) -> (12,10)
Info:                Sink serial.usb_fs_pe_inst.usb_fs_rx_inst.crc16_SB_DFFESS_Q_D_SB_LUT4_O_LC.CEN
Info:  0.1 23.6  Setup serial.usb_fs_pe_inst.usb_fs_rx_inst.crc16_SB_DFFESS_Q_D_SB_LUT4_O_LC.CEN
Info: 8.5 ns logic, 15.1 ns routing