{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"OpenROAD-flow-scripts","owner":"The-OpenROAD-Project","isFork":false,"description":"OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/","topicNames":["tcl","eda","rtl","verilog","def","gdsii","timing-analysis","openroad","lef","opendb-database"],"topicsNotShown":0,"allTopics":["tcl","eda","rtl","verilog","def","gdsii","timing-analysis","openroad","lef","opendb-database"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":38,"issueCount":76,"starsCount":268,"forksCount":264,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-20T02:29:28.433Z"}},{"type":"Public","name":"OpenROAD","owner":"The-OpenROAD-Project","isFork":false,"description":"OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/","topicNames":["cpp","tcl","eda","rtl","verilog","def","gdsii","timing-analysis","openroad","lef"],"topicsNotShown":1,"allTopics":["cpp","tcl","eda","rtl","verilog","def","gdsii","timing-analysis","openroad","lef","opendb-database"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":60,"issueCount":238,"starsCount":1357,"forksCount":482,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":[73,133,116,172,120,178,90,114,190,137,122,144,71,82,84,115,115,85,68,118,64,98,70,65,129,110,92,101,74,97,90,50,108,100,104,111,81,106,114,94,95,103,103,121,107,161,101,76,161,121,115,59],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-18T18:16:43.046Z"}},{"type":"Public","name":"LSOracle","owner":"The-OpenROAD-Project","isFork":true,"description":"IDEA project source files ","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":41,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-02T21:01:54.560Z"}},{"type":"Public","name":"actions-test","owner":"The-OpenROAD-Project","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":0,"starsCount":1,"forksCount":2,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-14T22:03:48.871Z"}},{"type":"Public","name":"asap7_sram_0p0","owner":"The-OpenROAD-Project","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-11-02T05:24:15.081Z"}},{"type":"Public","name":"micro2022tutorial","owner":"The-OpenROAD-Project","isFork":true,"description":"Website for the OpenROAD tutorial held at the MICRO 2022 conference","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":19,"forksCount":9,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-10-06T23:51:17.372Z"}},{"type":"Public archive","name":"RePlAce","owner":"The-OpenROAD-Project","isFork":false,"description":"RePlAce global placement tool","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":201,"forksCount":75,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-08-13T00:59:01.466Z"}},{"type":"Public archive","name":"PDNSim","owner":"The-OpenROAD-Project","isFork":false,"description":"Power grid analysis","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":13,"forksCount":6,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-08-05T14:55:54.085Z"}},{"type":"Public","name":"alpha-release","owner":"The-OpenROAD-Project","isFork":false,"description":"Builds, flow and designs for the alpha release","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":13,"starsCount":54,"forksCount":18,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2019-12-18T01:39:19.915Z"}}],"repositoryCount":9,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}