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As of now, those SoCs are not fully documented and only binary blobs avilable.
For reference:
The text was updated successfully, but these errors were encountered:
for the Duo S, the DDR controller registers are documented, just not how to use them
the SPI flash is memory mapped EMMC DAT 0 and 3 determine the boot source dat3 down, dat 0 up means boot from SPI NOR flash
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As of now, those SoCs are not fully documented and only binary blobs avilable.
For reference:
The text was updated successfully, but these errors were encountered: