Feature request (not for CV32E40P): Implement external flush handshake for FENCE.I

[Silabs-ArjanB]

As CV32E40P does not have internal cache(s) the FENCE.I instruction only flushes the internal pipeline and prefetch buffer. For systems with an external (non-coherent) cache a 'software-directed cache-flushing followed by a FENCE.I instruction' can be used to achieve the desired effect (as described in #328).

For future cores (not CV32E40P) this feature request is to add an external interface (flush_req_o, flush_ack_i) which will get triggered by a FENCE.I instruction and can therefore be used to implement hardware-based flushing of external caches. The flush_ack_i would then be used to prevent any instruction fetch after the FENCE.I until the acknowledge is provided.