-
Notifications
You must be signed in to change notification settings - Fork 388
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Possible inferred latches in riscv_pmp.sv #293
Comments
I have checked my synthesis trials and there are no warnings about Based on the Genus default settings, a latch whose output never changes is replaced by the corresponding constant value (optimize_constant_latches is true). I've found only one warning about always_comb not matching the expected behaviour, but it looks like this thing is related to a different module:
|
Looking at the code indeed it is not a Latch. Maybe writing them to |
Agreed, I don't see a latch. I would recommend using: and removing all duplicate assignments to 0, unless you want them for clarity. This will simplify the code greatly and hopefully git rid of the bogus latch warning. |
I had a hunch that the for loop might be the problem. If N_PMP_ENTRIES is 0, none of the subsequent code is executed and data_match_region is not updated. I added this:
Which I believe is standard practice for combinational logic. The warning disappeared. That said, I will discuss the validity of the warning with our R&D team at Metrics. Thanks for reporting the issue! |
I was going through some Genus documentation and found that the tool may give an error in case |
Hi @ludmila-bta, do you mean something like this:
I think this is a good suggestion. It appears to be logically equivalent and should eliminate the inferred latch. On the other hand, the suggestion from @aimeepsutton should also eliminate the latch and @GTumbush pointed out it allows for some code simplification. Either way, I'm more convinced than before that this is something that needs to be fixed. |
Hi @MikeOpenHWGroup. Yes, this is exactly what Cadence recommends as a tool friendly coding. Or another solution would be something like
I've found it in their description of how to resolve the VLOGPT-46 error : I am still not sure why the tool didn't complain about this one in my trials. Would be good to debug it, but unfortunately I don't have the license anymore. I can send this question to our Genus AE if you think it would be beneficial. |
DSIM is giving a warning about inferred latches in riscv_pmp.sv. I do not see this warning with xrun, and I lack sufficient understanding of synthesis to determine if this warning is real or not.
I'm assigning this issue to @davideschiavone because he knows the code well, @aimeepsutton because she knows DSIM and @ludmila-bta because she is a synthesis expert.
Details below:
URL: https://github.com/openhwgroup/cv32e40p
Branch: master
Hash: de82624
Path: rtl/riscv_pmp.sv, lines 575..640
Below is the snipit of code for the first warning. DSIM warns about an inferred latch on
data_match_region
. A similar snipit of code generates the same warning aboutinstr_match_region
. Note that there are similar warnings in other RTL files which I have not yet investigated.It seems to me that
data_match_region
is written on every path through the code, but I do not know if synthesis will see it that way.To Reproduce:
Run the
comp
rule (clones the RTL, compiles, and quits).The text was updated successfully, but these errors were encountered: