TODOs

[munroesj52]

1. Rotate left/right byte,/halfword/word/doubleword/quadword immediate. Done
2. Rotate reft/right doubleword/quadword. Done
3. max and min for doubleword and quadword Done
4. Absolute Difference Unsigned halfword|word|doubleword|quadword Done
5. BCD compare, min, max: Signed BCD compare "Done"
6. BCD <-> Zoned converts Done
7. Count trailing zeros Done
8. Merge even/odd for byte/halfword/word/doubleword across POWER7/8/9. Done

[munroesj52]

Publish the floating headers: vec_f32_ppc.h vec_f64_ppc.h, and vec_f128_ppc.h. Done.

0. Also vec-f16_ppc.h?
   Converts f16 <-> f32?
   Basic operations on f16?
1. SIMD Predicate isnan, isinf, isfinite, isnormal? Done
2. SIMD convert smaller <-> larger float
3. SIMD convert float <-> int
   include float128 and __int128
4. SIMD copysign and signbit predicate
5. Merge algebraic high/low for byte/halfword/word/doubleword. Similar to merge even/odd, but not messed up by endian. This can be used for multiple byte/halfword modulo as well as the multiply byte/halfword/word/doubleword high. The multiply high is needed to support multiplicative inverse (integer divide via multiply/shift via carefully chosen constants). Done
6. Vector BCD arithmetic and conversions Done

[munroesj52]

Update the main-page documentation. One specific issue is the vec_isnanf32 example the under Performance data. The current POWER9 implementation uses the vec_test_data_class operation (xvtstdcsp) and that should be included in the example.