v2.7.2

This is a patch release containing the following changes to v2.7.1:

• Fixed segfaults in deconvolution backpropagation with ACL on AArch64-based processors (f02e6f3)
• Fixed code generation issues in Intel AVX2 convolution implementation (2ba2523, b60633f, 844326b, 2009164)
• Fixed correcteness issues and runtime errors in deconvolution with binary post-ops on Intel GPUs (dd54d39)
• Improved performance of convolutions with small number of channels and large spatial sizes on systems with Intel AMX (26f97dc, 4cb648d)
• Fixed runtime error in int8 convolutions with groups on Xe architecture based GPUs (e5a70f4)
• Improved inner product weight gradient performance on Xe architecture based GPUs (9e9b859, 12ec4e3)
• Improved batch normalization performance with threadpool threading (4fd5ab2)
• Improved inner product performance with binary post-ops in broadcast mode on Intel CPUs (d43c70d, 49ca4e1)
• Fixed segfaults and correctness issues in sum primitive with threadpool threading (ee7a321)
• Extended persistent cache API to cover engine objects (58481d6, 5f69dad, 16c0a95, 068071b)
• Added support for newer versions of Intel GPU drivers (7144393)
• Updated ITT API version to 3.23.0 (d23cc95)
• Fixed convolution correctness issue on Intel Data Center GPU Flex Series (365ac20)
• Fixed fp64 convolution correctness issue on Intel Data Center GPU MAX Series (9d4bf94, 6705403)
• Fixed correctness issues in reduction primitive with binary post-op on Intel GPUs (ae9d075, e3b80c5)
• Improved convolution performance on on Intel Data Center GPU MAX Series (90be8d5, caf4863)
• Fixed build errors with ONEDNN_ENABLE_PRIMITIVE_GPU_ISA build option (de2db04)
• Fixed correctness issues in convolution with per-tensor binary post-ops on Intel CPUs (9cf9c18)
• Improved convolution performance on Intel Data Center GPU Flex Series (8b08a07)

graph-v0.7.1

This is a patch release containing the following changes to graph-v0.7:

• Fixed a build issue in compiler backend (70258d3)
• Optimized for zero points folding (d6f12b5)
• Fixed a primitive descriptor cache issue in reorder fusion (0887652)

v2.7.1

This is a patch release containing the following changes to v2.7:

• Fixed performance regression for batch normalization primitive in TBB and threadpool configurations (cd953e4)
• Improved grouped convolution performance on Xe Architecture GPUs (d7a781e, cb1f3fe, 4e84474, 7ba3c40)
• Fixed runtime error in int8 reorder on Intel GPUs (53532a9)
• Reverted MEMFD allocator in Xbyak to avoid segfaults in high load scenarios (3e29ae2)
• Fixed a defect with incorrect caching of BRGEMM-based matmul primitive implementations with trivial dimensions (87cd979)
• Improved depthwise convolution performance with per-tensor binary post-ops for Intel CPUs (f430a5a)
• Extended threadpool API to manage maximum concurrency (8a1e959, 64e5594)
• Fixed potential integer overflow in BRGEMM-based convolution implementation (25ccee3)
• Fixed performance regression in concat primitive with any format on Intel CPUs (2a60ade, feb614d)
• Fixed compile-time warnings in matmul_perf example (b5faa77)
• Fixed 'insufficient registers in requested bundle' runtime error in convolution primitive on Xe Architecture GPUs (4c9d46a)
• Addressed performance regression for certain convolution cases on Xe Architecture GPUs (f28b58a, 18764fb)
• Added support for Intel DPC++/C++ Compiler 2023 (c3781c6, a1a8952, 9bc87e6, e3b1987)
• Fixed int8 matmul and inner product performance regression on Xe Architecture GPUs (3693fbf, c8adc17)
• Fixed accuracy issue for convolution, inner product and matmul primitives with tanh post-op on Xe Architecture GPUs (88b4e57, 83ce6d2, 6224dc6, 10f0d0a)
• Suppressed spurious build warnings with GCC 11 (44255a8)

v2.6.3

This is a patch release containing the following changes to v2.6.2:

• Fixed potential integer overflow in BRGEMM-based convolution implementation (deb5595)
• Fixed a defect with incorrect caching of BRGEMM-based matmul primitive implementations with trivial dimensions (305bed5)
• Extended benchdnn performance benchmarking capabilities on GPU with device-side performance measurement mode (ba86325)
• Fixed segfault in pooling primitive on CPUs (689d874)

graph-v0.7

This is the Beta Update release for oneDNN Graph API based on oneDNN v2.7 release.

Functionality

• Added operations Select, LogicalAnd, LogicalOr, LogicalXor, LogicalNot, Greater, GreaterEqual, Equal, NoeEqual, Less, and LessEqual.
• Added boolean data type to support logical operations.
• Added support for passing compilation context to the compile API. This feature allows passing additional information, like tensor shape context, for the backend to generate better kernel code.
• Introduced convolution block fusion via oneDNN Graph Compiler.
• Experimental: Introduced dynamic shapes support for multi-level perceptron (MLP) block via oneDNN Graph Compiler.

Known Issues and Limitations

• The weight’s opaque layout can be queried only from a compiled partition, which requires that input tensor shapes must be known at compilation time.
• MHA and MLP fusion are not activated on machines without Intel AVX-512 support.

Thanks to the Contributors

This release contains contributions from the project core teams as well as Jiong Gong, Chunyuan Wu, Sanchit Jain, Yiqiang Li, Yunfei Mao, Kiefer Kuah and others.

graph-v0.6

This is the Beta release for oneDNN Graph based on oneDNN v2.7 release.

Functionality

• Introduced FP32, BF16, FP16, and INT8 inference support on GPU.
• Introduced FP32 and BF16 training support on GPU.
• Introduced support for floating point math mode at graph construction phase. The mode allows the implementation to use low precision datatype for computations when possible.
• Added graph::finalize() function to indicate that the user has finished adding operations into the graph and the graph is ready for partitioning.
• Added operations AbsBackprop, Mish, MishBackprop, and LeakyReLU.
• Updated API and operation definitions to comply with oneDNN Graph Specification 1.0-beta.

Usability

• Integrated Graph component headers, source and build system into oneDNN:
  • Headers moved to include/oneapi/dnnl.
  • Source moved to src/graph.
  • Graph functionality is included into single shared object or dynamic library produced by the build system.
• Aligned API with oneDNN:
  • Shared common dnnl::engine and dnnl::stream. The original dnnl::graph::engine and dnnl::graph::stream API were removed.
  • Added a new make_engine_with_allocator() API to create dnnl::engine with dnnl::graph::allocator.
  • A few common basic types were shared between oneDNN and oneDNN Graph, including dnnl_status_t, dnnl_data_type_t, and dnnl_dims_t, etc.
• Introduced ONEDNN_BUILD_GRAPH build option to manage Graph component build.

Validation

• Introduced ONEDNN_GRAPH_DUMP environment variable that serialized library graph and subgraph into JSON files.
• Added the initial version of benchdnn graph driver which can be used to benchmark the performance with a dumped graph JSON file.

Breaking changes

• Removed operations HardTanh, Index, Pow, etc. Please check the operation kind list for details.

Known Issues and Limitations

• Graph Compiler component is not included with this release. It will be reinstated in oneDNN Graph Beta Update release.
• The weight’s opaque layout can be queried only from a compiled partition, which requires that input tensor shapes must be known at compilation time.
• Build option ONEDNN_BUILD_GRAPH is not compatible with some of the build options supported by the build system including ONEDNN_GPU_RUNTIME=OCL, ONEDNN_ENABLE_WORKLOAD=INFERENCE, ONEDNN_ENABLE_PRIMITIVE, and others.

Thanks to the Contributors

This release contains contributions from the project core teams as well as Jiong Gong, Chunyuan Wu, Sanchit Jain, Yiqiang Li, Yunfei Mao, Kiefer Kuah and others.

v2.7

Performance Optimizations

• Intel Architecture Processors
  • Improved performance for future Intel Xeon Scalable processors (code name Sapphire Rapids).
  • Introduced performance optimizations for bf16 floating point math mode on Intel Xeon Scalable processors (code name Sapphire Rapids). The bf16 math mode allows oneDNN to use bf16 arithmetic and Intel AMX instructions in computations on fp32 data.
• Intel Graphics Products
  • Improved performance for future Xe Architecture graphics (code name Ponte Vecchio).
  • Introduced performance optimizations for tf32 floating point math mode on future Xe Architecture graphics (code name Ponte Vecchio). The tf32 math mode allows oneDNN to use tf32 arithmetic in computations on fp32 data.
  • Improved performance for Intel Arc graphics (formerly Alchemist and DG2) and Intel Data Center GPU Flex Series (formerly Arctic Sound-M)
• AArch64-based Processors
  • Improved convolution and binary primitive performance for processors with SVE 512 support.
  • Improved shuffle and eltwise primitives performance for processors with SVE 256 and SVE 128 support.
  • Improved PReLU, batch normalization, and pooling primitives performance via Compute Library for the Arm Architecture (ACL).
  • Improved performance of inner product, matmul, convolution, and batch norm primitives with post-ops via ACL.
• PowerPC64-based Processors
  • Introduced performance optimizations for int8 and bfloat16 GEMM.

Functionality

• Introduced runtime output scales support in all primitives.
• Introduced scales support in concat primitive.
• Extended floating point math mode API with tf32 data type option.
• Extended eltwise primitive with support for hardsigmoid algorithm.
• Extended layer normalization primitive with support for mixed source and destination data types.
• Extended depthwise post-op with support for arbitrary padding size. The implementation is available only on Intel processors.
• Added limited fp64 data type support in convolution primitive. Optimized implementation is available for future Xe Architecture graphics (code name Ponte Vecchio).
• Extended int8 convolution and deconvolution implementations on GPUs with arbitrary destination data type support.
• Extended batch normalization primitive with dnnl_fuse_norm_add_relu flag that allows to fuse sum and relu operations. The implementation is available for Intel GPUs.
• Extended GPU deconvolution primitive implementation with support for output scales and zero points.
• Introduced threadpool threading support for AArch64-based processors.
• Introduced Unified Shared Memory (USM) support for SYCL backend on NVIDIA GPUs.
• Introduced initial support for AMD GPUs via MIOpen library. Supported primitives include Local Response Normalization (LRN), softmax, and eltwise.

Usability

• Added matmul_perf example that benchmarks matmul primitive for all supported data types.
• Introduced annotations for JIT kernels to allow profilers like Linux perf to correctly label JIT code.
• Extended verbose logs converter with RNN primitive support.
• Added verbose output for dnnl_*gemm* calls.
• Removed Level Zero headers from the list of build time dependencies.
• Adjusted NVIDIA GPU implementation to comply with oneDNN numerical behavior. Implicit downconvert to fp16 and tf32 are now managed via math mode API.

Validation

• Added benchdnn driver for validation of internal BRGEMM implementation.
• Improved benchdnn reference implementation performance with threadpool threading model.
• Extended benchdnn performance benchmarking capabilities on GPU with device-side performance measurement mode (mode=po).

Deprecated Functionality

• Support for SYCL 1.2.1 (aka SYCL 2017 standard) is deprecated and will be removed in the future releases.
• Static output scales are deprecated and will be removed in the next release.
• Convolution Winograd algorithm implementation for int8 data type is deprecated and will be removed in the next release.

Breaking Changes

• Changed formula for AUGRU RNN cell to align with Tensorflow. See proposal for details.

Thanks to the Contributors

This release contains contributions from the project core team as well as Aidan Belton @AidanBeltonS, @akshatasangelkar, Alex Bojan @lb991, Crefeda Rodrigues @cfRod, Damian Szwichtenberg @dszwicht, Diana Bite @diaena, Divakar Mariyanna @bmdivakar, Emilio Cota @cota, Gordon Fossum @austinpagan, Hugh Delaney @hdelan, Jacek Czaja @jczaja, @jakpiase, Jonathan Deakin @jondea, Kentaro Kawakami @kawakami-k, Kotha Sowmya @Sowmyakotha1999, Louie Tsai @louie-tsai, Mark Ryan @markdryan, MITSUNARI Shigeo @herumi, Mona Minakshi @monaminakshi, @NaNAGISaSA, Nathan John Sircombe @nSircombe, Peter Caday @petercad, @pgorlani, Sreekanth Yalachigere @sreekanth-yalachigere, Tadej Ciglarič @t4c1, and Thiago Macieira @thiagomacieira. We would also like to thank everyone who asked questions and reported issues.

v2.7-rc

This is a release candidate for oneDNN v2.7. Please provide feedback and submit defect reports via Github issues.

Performance Optimizations

• Intel Architecture Processors
  • Improved performance for future Intel Xeon Scalable processors (code name Sapphire Rapids).
  • Introduced performance optimizations for bf16 floating point math mode on Intel Xeon Scalable processors (code name Sapphire Rapids). The bf16 math mode allows oneDNN to use bf16 arithmetic and Intel AMX instructions in computations on fp32 data.
• Intel Graphics Products
  • Improved performance for future Xe Architecture graphics (code name Ponte Vecchio).
  • Introduced performance optimizations for tf32 floating point math mode on future Xe Architecture graphics (code name Ponte Vecchio). The tf32 math mode allows oneDNN to use tf32 arithmetic in computations on fp32 data.
  • Improved performance for Intel Arc graphics (formerly Alchemist and DG2) and Intel Data Center GPU Flex Series (formerly Arctic Sound-M)
• AArch64-based Processors
  • Improved convolution and binary primitive performance for processors with SVE 512 support.
  • Improved eltwise and shuffle primitives performance for processors with SVE 256 and SVE 128 support.
  • Improved PReLU, batch normalization, and pooling primitives performance via Compute Library for the Arm Architecture (ACL).
  • Improved performance of inner product, matmul, convolution, and batch norm primitives with post-ops via ACL.
• PowerPC64-based Processors
  • Introduced performance optimizations for int8 and bfloat16 GEMM.

Functionality

• Introduced runtime output scales support in all primitives.
• Introduced scales support in concat primitive.
• Extended floating point math mode API with tf32 data type option.
• Extended eltwise primitive with support for hardsigmoid algorithm.
• Extended layer normalization primitive with support for mixed source and destination data types.
• Extended depthwise post-op with support for arbitrary padding size. The implementation is available only on Intel processors.
• Added limited fp64 data type support in convolution primitive. Optimized implementation is available for future Xe Architecture graphics (code name Ponte Vecchio).
• Extended int8 convolution and deconvolution implementations on GPUs with arbitrary destination data type support.
• Extended batch normalization primitive with dnnl_fuse_norm_add_relu flag that allows to fuse sum and relu operations. The implementation is available for Intel GPUs.
• Extended GPU deconvolution primitive implementation with support for output scales and zero points.
• Introduced threadpool threading support for AArch64-based processors.
• Introduced Unified Shared Memory (USM) support for SYCL backend on NVIDIA GPUs.
• Introduced initial support for AMD GPUs via MIOpen library. Supported primitives include Local Response Normalization (LRN), softmax, and eltwise.

Usability

• Introduced annotations for JIT kernels to allow profilers like Linux perf to correctly label JIT code.
• Extended verbose logs converter with RNN primitive support.
• Added verbose output for dnnl_*gemm* calls.
• Removed Level Zero headers from the list of build time dependencies.
• Adjusted NVIDIA GPU implementation to comply with oneDNN numerical behavior. Implicit downconvert to fp16 and tf32 are now managed via math mode API.

Validation

• Added benchdnn driver for validation of internal BRGEMM implementation.
• Improved benchdnn reference implementation performance with threadpool threading model.
• Extended benchdnn performance benchmarking capabilities on GPU with device-side performance measurement mode (mode=po).

Deprecated Functionality

• Support for SYCL 1.2.1 (aka SYCL 2017 standard) is deprecated and will be removed in the future releases.
• Static output scales are deprecated and will be removed in the next release.
• Convolution Winograd algorithm implementation for int8 data type is deprecated and will be removed in the next release.

Breaking Changes

• Changed formula for AUGRU RNN cell to align with Tensorflow. See proposal for details.

Thanks to the Contributors

This release contains contributions from the project core team as well as Aidan Belton @AidanBeltonS, @akshatasangelkar, Alex Bojan @lb991, Crefeda Rodrigues @cfRod, Damian Szwichtenberg @dszwicht, Diana Bite @diaena, Divakar Mariyanna @bmdivakar, Emilio Cota @cota, Gordon Fossum @austinpagan, Hugh Delaney @hdelan, Jacek Czaja @jczaja, @jakpiase, Jonathan Deakin @jondea, Kentaro Kawakami @kawakami-k, Kotha Sowmya @Sowmyakotha1999, Louie Tsai @louie-tsai, Mark Ryan @markdryan, MITSUNARI Shigeo @herumi, Mona Minakshi @monaminakshi, @NaNAGISaSA, Nathan John Sircombe @nSircombe, Peter Caday @petercad, @pgorlani, Sreekanth Yalachigere @sreekanth-yalachigere, Tadej Ciglarič @t4c1, and Thiago Macieira @thiagomacieira. We would also like to thank everyone who asked questions and reported issues.

v2.6.2

This is a patch release containing the following changes to v2.6.1:

• Removed unused variables (2500b0f, b4e0032)
• Fixed correctness issue in fp32 convolution implementation for cases with large spatial size (207af06)
• Fixed correctness issue in bfloat16 matmul implementation for processors with Intel AMX support (404b762)
• Fixed correctness issue in int8 reorder implementation with zero points (b340cba)
• Improved int8 matmul and inner product primitives performance with small matrices for processors with Intel AMX support (73b7572, 58b386a)
• Improved int8 convolution performance for processors with Intel DL Boost support (f35a62f)
• Aligned AUGRU formula with Tensorflow definition (e47c6c5, 4ba0a57, b311e24)
• Suppressed 'unvectorized loop' warning for Intel C/C++ Compiler (3932d04)

graph-v0.5.2

This is a patch release containing the following changes to graph-v0.5.1:

• Deprecated quantized ReLU fusion patterns (85405a9)