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POWERARMTraceBuilder.tcc
2341 lines (2259 loc) · 83.1 KB
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POWERARMTraceBuilder.tcc
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/* Copyright (C) 2015-2017 Carl Leonardsson
*
* This file is part of Nidhugg.
*
* Nidhugg is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Nidhugg is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see
* <http://www.gnu.org/licenses/>.
*/
#include "Debug.h"
#include "POWERARMTraceBuilder.h"
#include <cassert>
namespace PATB_impl{
template<MemoryModel MemMod,CB_T CB,class Event>
TB<MemMod,CB,Event>::TB(const Configuration &conf)
: POWERARMTraceBuilder(conf),
sched_count(0), fetch_count(0),
uncommitted_nonblocking_count(0),
is_aborted(false),
next_clock_index(0),
TRec(&cpids)
{
fch.emplace_back();
threads.emplace_back();
cpids.emplace_back();
}
template<MemoryModel MemMod,CB_T CB,class Event>
TB<MemMod,CB,Event>::~TB(){
}
template<MemoryModel MemMod,CB_T CB,class Event>
Trace *TB<MemMod,CB,Event>::get_trace() const{
std::vector<Error*> errs;
for(unsigned i = 0; i < errors.size(); ++i){
if(error_is_real(*errors[i])){
errs.push_back(errors[i]->clone());
}
}
std::vector<PATrace::Evt> evts(prefix.size());
for(unsigned i = 0; i < prefix.size(); ++i){
evts[i].iid = prefix[i];
evts[i].param.choices = get_evt(prefix[i]).cur_param.choices;
// Ignore the rest of the parameter (relations etc.)
}
return new PATrace(evts, cpids, conf, errs, TRec.to_string(2),
!sleepset_is_empty());
}
template<MemoryModel MemMod,CB_T CB,class Event>
int TB<MemMod,CB,Event>::spawn(int proc){
assert(0 <= proc && proc < int(cpids.size()));
fch.emplace_back();
threads.emplace_back();
cpids.push_back(CPS.spawn(cpids[proc]));
return int(fch.size())-1;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::abort(){
is_aborted = true;
}
template<MemoryModel MemMod,CB_T CB,class Event>
IID<int> TB<MemMod,CB,Event>::fetch(int proc,
int load_count,
int store_count,
const VecSet<int> &addr_deps,
const VecSet<int> &data_deps){
assert(0 <= proc && proc < int(threads.size()));
assert(threads.size() <= fch.size());
Thread &T = threads[proc];
Event *evt;
if(T.fch_count < int(fch[proc].size())){
evt = &fch[proc][T.fch_count];
switch(evt->filled_status){
case Event::STATUS_EMPTY:
*evt = Event(load_count,store_count,addr_deps,data_deps,
threads[proc].last_fetched_eieio_idx,
threads[proc].last_fetched_lwsync_idx,
threads[proc].last_fetched_sync_idx,
next_clock_index++);
break;
case Event::STATUS_PARAMETER:
{
Param P = std::move(evt->cur_param);
Branch B = std::move(evt->cur_branch);
VecSet<Branch> new_branches(std::move(evt->new_branches));
assert(evt->new_params.empty());
int branch_start = evt->branch_start;
int branch_end = evt->branch_end;
PAEvent::RecalcParams recalc_params = evt->recalc_params;
IID<int> recalc_params_load_src = evt->recalc_params_load_src;
*evt = Event(load_count,store_count,addr_deps,data_deps,
threads[proc].last_fetched_eieio_idx,
threads[proc].last_fetched_lwsync_idx,
threads[proc].last_fetched_sync_idx,
next_clock_index++);
evt->cur_param = std::move(P);
evt->cur_branch = std::move(B);
evt->new_branches = std::move(new_branches);
evt->branch_start = branch_start;
evt->branch_end = branch_end;
evt->recalc_params = recalc_params;
evt->recalc_params_load_src = recalc_params_load_src;
break;
}
case Event::STATUS_COMPLETE:
assert(evt->load_count == load_count);
assert(evt->has_load == (0 < load_count));
assert(evt->has_store == (0 < store_count));
evt->unknown_addr_count = load_count + store_count;
evt->unknown_data_count = store_count;
assert(evt->addr_deps == addr_deps);
assert(evt->data_deps == data_deps);
assert(evt->eieio_idx_before == threads[proc].last_fetched_eieio_idx);
assert(evt->lwsync_idx_before == threads[proc].last_fetched_lwsync_idx);
assert(evt->sync_idx_before == threads[proc].last_fetched_sync_idx);
evt->eieio_idx_after = -1;
evt->lwsync_idx_after = -1;
evt->sync_idx_after = -1;
evt->accesses.clear();
evt->accesses.reserve(load_count+store_count);
evt->accesses.resize(load_count,Access(Access::LOAD));
evt->accesses.resize(load_count+store_count,Access(Access::STORE));
evt->baccesses.clear();
evt->access_tgts.clear();
evt->clock_index = next_clock_index++;
evt->cb_bwd.clear();
evt->cb_bwd.set(evt->clock_index);
evt->poloc_bwd_computed = false;
assert(evt->recalc_params == PAEvent::RECALC_NO);
break;
}
}else{
assert(T.fch_count == int(fch[proc].size()));
fch[proc].emplace_back(load_count,store_count,addr_deps,data_deps,
threads[proc].last_fetched_eieio_idx,
threads[proc].last_fetched_lwsync_idx,
threads[proc].last_fetched_sync_idx,
next_clock_index++);
evt = &fch[proc].back();
}
++fetch_count;
++uncommitted_nonblocking_count;
++T.fch_count;
evt->iid = IID<int>(proc,T.fch_count);
evt->ctrl_deps = T.ctrl_deps;
evt->ctrl_isync_deps = T.ctrl_isync_deps;
update_addr_known_prefix(proc);
return evt->iid;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::register_addr(const IID<int> &iid, Accid a, const MRef &addr){
Event &evt = get_evt(iid);
assert(0 <= a && a < Accid(evt.accesses.size()));
assert(!evt.accesses[a].addr_known);
evt.accesses[a].addr = addr;
evt.accesses[a].addr_known = true;
--evt.unknown_addr_count;
/* Add the corresponding byte accesses */
for(int i = 0; i < addr.size; ++i){
void *p = (void*)&((char*)addr.ref)[i];
evt.access_tgts.insert(p);
if(evt.accesses[a].type == Access::LOAD){
/* Check if there already is a load to that byte. */
bool do_insert = true;
for(int i = 0; do_insert && i < evt.load_count; ++i){
if(i == a) continue;
if(evt.accesses[i].addr_known &&
evt.accesses[i].addr.includes(p)){
do_insert = false;
}
}
if(do_insert){
evt.baccesses.emplace_back(ByteAccess::LOAD,p);
}
}else{
assert(evt.accesses[a].type == Access::STORE);
char d;
if(evt.accesses[a].data_known){
d = ((char*)evt.accesses[a].data.get_block())[i];
}
int i = int(evt.accesses.size()-1);
while(evt.load_count <= i &&
!(i != a &&
evt.accesses[i].addr_known &&
evt.accesses[i].addr.includes(p))) --i;
if(i < evt.load_count){ // No other store to this byte (yet)
/* Insert the store */
if(evt.accesses[a].data_known){
evt.baccesses.emplace_back(p,d);
}else{
evt.baccesses.emplace_back(ByteAccess::STORE,p);
}
}else if(i < a){ // This store overwrites the previous
if(evt.accesses[a].data_known){
/* Find the byte access, and update the data */
int j = 0;
while(!(evt.baccesses[j].type == ByteAccess::STORE &&
evt.baccesses[j].addr == p)) ++j;
evt.baccesses[j].data = d;
evt.baccesses[j].data_known = true;
}// else, data will be stored when it is registered
} // else, this store is overwritten by the later store (do nothing)
}
}
update_addr_known_prefix(iid.get_pid());
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::register_data(const IID<int> &iid, Staccid a, const MBlock &data){
Event &evt = get_evt(iid);
assert(evt.load_count <= a && a < int(evt.accesses.size()));
assert(evt.accesses[a].type == Access::STORE);
assert(!evt.accesses[a].data_known);
evt.accesses[a].data = data;
evt.accesses[a].data_known = true;
--evt.unknown_data_count;
/* Possibly update data in byte accesses */
if(!evt.accesses[a].addr_known) return; // Byte accesses do not yet exist.
for(int i = 0; i < evt.accesses[a].addr.size; ++i){
void *p = (void*)&((char*)evt.accesses[a].addr.ref)[i];
bool data_written = false;
/* Search for other stores to the same byte */
for(int j = int(evt.accesses.size())-1; a < j; --j){
if(evt.accesses[j].addr_known &&
evt.accesses[j].addr.includes(p)){
data_written = true; // Access j overwrites this store (Do nothing)
break;
}
}
/* Find and update the byte access */
for(unsigned j = 0; !data_written && j < evt.baccesses.size(); ++j){
if(evt.baccesses[j].type == ByteAccess::STORE &&
evt.baccesses[j].addr == p){
evt.baccesses[j].data_known = true;
evt.baccesses[j].data = ((char*)data.get_block())[i];
data_written = true;
}
}
assert(data_written);
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::register_load_requirement(const IID<int> &iid, Ldaccid a, ldreqfun_t *f){
Event &evt = get_evt(iid);
assert(0 <= a && a < evt.load_count);
assert(!evt.accesses[a].load_req);
if(!evt.has_load_req()){
/* The event is blocking, but was previously counted as nonblocking. */
--uncommitted_nonblocking_count;
}
evt.accesses[a].load_req = f;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::fetch_ctrl(int proc, const VecSet<int> &deps){
assert(0 <= proc && proc < int(threads.size()));
threads[proc].ctrl_deps.insert(deps);
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::fetch_fence(int proc, FenceType type){
const int idx = threads[proc].fch_count;
switch(type){
case ISYNC:
threads[proc].ctrl_isync_deps.insert(threads[proc].ctrl_deps);
threads[proc].ctrl_deps.clear();
break;
case EIEIO:
for(int i = std::max(0,threads[proc].last_fetched_eieio_idx); i < idx; ++i){
fch[proc][i].eieio_idx_after = idx;
}
threads[proc].last_fetched_eieio_idx = idx;
break;
case LWSYNC:
for(int i = std::max(0,threads[proc].last_fetched_lwsync_idx); i < idx; ++i){
fch[proc][i].lwsync_idx_after = idx;
}
threads[proc].last_fetched_lwsync_idx = idx;
break;
case SYNC:
for(int i = std::max(0,threads[proc].last_fetched_sync_idx); i < idx; ++i){
fch[proc][i].sync_idx_after = idx;
}
threads[proc].last_fetched_sync_idx = idx;
break;
default:
throw std::logic_error("POWERARMTraceBuilder::fetch_fence: Unknown type of fence.");
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
bool TB<MemMod,CB,Event>::committable(Event &evt){
const int proc = evt.iid.get_pid();
if(evt.committed) return false;
/* Check dependencies */
if(!evt.all_addr_and_data_known()) return false;
#ifndef NDEBUG
for(int i : evt.addr_deps){
assert(fch[proc][i-1].committed);
}
for(int i : evt.data_deps){
assert(fch[proc][i-1].committed);
}
for(const Access &A : evt.accesses){
assert(A.satisfied());
}
for(const ByteAccess &A : evt.baccesses){
assert(A.satisfied());
}
#endif
if(CB == CB_ARM || CB == CB_POWER){
/* Check addr;po */
if(threads[proc].addr_known_prefix < evt.iid.get_index()) return false;
}
if(CB == CB_ARM || CB == CB_POWER){
/* Check sync and lwsync */
if(threads[proc].committed_prefix < evt.sync_idx_before) return false;
if(threads[proc].committed_prefix < evt.lwsync_idx_before) return false;
}
if(CB == CB_POWER){
/* Check poloc */
compute_poloc_bwd(evt);
for(const IID<int> &iid : evt.rel.poloc.bwd){
if(!get_evt(iid).committed) return false;
}
}
return true;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::update_committed_prefix(int proc){
while(threads[proc].committed_prefix < threads[proc].fch_count &&
fch[proc][threads[proc].committed_prefix].committed){
++threads[proc].committed_prefix;
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::update_addr_known_prefix(int proc){
while(threads[proc].addr_known_prefix < threads[proc].fch_count &&
fch[proc][threads[proc].addr_known_prefix].unknown_addr_count == 0){
++threads[proc].addr_known_prefix;
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
bool TB<MemMod,CB,Event>::schedule(IID<int> *iid, std::vector<MBlock> *values){
if(is_aborted) return false;
/* Schedule */
if(sched_count < int(prefix.size())){
/* The schedule is decided already by prefix */
const int proc = prefix[sched_count].get_pid();
Event &evt = get_evt(prefix[sched_count]);
assert(committable(evt));
if(!commit(evt,values,true)){
/* The branch failed: The fixed load source is not allowed. */
assert((prefix[evt.branch_end] == evt.iid) ||
(prefix[evt.branch_end-1] == evt.iid));
return false;
}
*iid = prefix[sched_count];
update_committed_prefix(proc);
++sched_count;
return true;
}else{
/* Find something new to schedule */
for(unsigned proc = 0; proc < threads.size(); ++proc){
const int fch_count = threads[proc].fch_count;
for(int idx = threads[proc].committed_prefix; idx < fch_count; ++idx){
if(committable(fch[proc][idx])){
if(commit(fch[proc][idx],values,false)){
*iid = IID<int>(proc,idx+1);
while(threads[proc].committed_prefix < threads[proc].fch_count &&
fch[proc][threads[proc].committed_prefix].committed){
++threads[proc].committed_prefix;
}
prefix.push_back(*iid);
++sched_count;
return true;
}else{
// The event is blocked. Do nothing, instead execute the
// next committable event.
}
}
}
}
}
return false;
}
template<MemoryModel MemMod,CB_T CB,class Event>
bool TB<MemMod,CB,Event>::commit(Event &evt, std::vector<MBlock> *values, bool replay){
if(!replay || evt.recalc_params != PAEvent::RECALC_NO){
populate_parameters(evt);
if(evt.recalc_params == PAEvent::RECALC_LOAD){
/* Filter parameters to remove all that do not read from the
* store event indicated by evt.recalc_params_load_src.
*/
std::vector<Param> ps = evt.new_params;
evt.new_params.clear();
for(const Param &P : ps){
if(P.rel.rf.bwd.count(evt.recalc_params_load_src)){
evt.new_params.push_back(P);
}
}
}else if(evt.recalc_params == PAEvent::RECALC_PARAM){
/* Find the parameter corresponding to cur_param */
bool found = false;
for(unsigned i = 0; i < evt.new_params.size(); ++i){
if(evt.new_params[i] == evt.cur_param){
evt.new_params[0] = evt.new_params[i];
evt.new_params.resize(1); // Remove all other parameters
found = true;
break;
}
}
if(!found){
evt.new_params.clear(); // No available parameter
}
}
/* Is there any allowed parameter? */
if(evt.new_params.empty()){
detect_rw_conflicts(evt);
return false;
}
/* Choose a parameter */
evt.cur_param = evt.new_params.back();
evt.new_params.pop_back();
evt.recalc_params = PAEvent::RECALC_NO;
}
/* Setup relations */
setup_relations_cur_param(evt);
/* Assign read values */
get_cur_load_values(evt,values);
/* Update mem */
assert(evt.baccesses.size() == evt.cur_param.choices.size());
for(unsigned i = 0; i < evt.baccesses.size(); ++i){
const ByteAccess &A = evt.baccesses[i];
mem[A.addr].commit(evt,A,evt.cur_param.choices[i]);
}
/* Identify conflicts with earlier loads */
detect_rw_conflicts(evt);
evt.committed = true;
if(TRec.is_active()){
TRec.trace_commit(evt.iid,evt.cur_param,evt.accesses,evt.baccesses,*values);
}
if(!evt.has_load_req()){ // evt is nonblocking...
--uncommitted_nonblocking_count; // ... but no longer uncommitted
}
return true;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::setup_relations_cur_param(Event &evt){
evt.rel = evt.cur_param.rel;
return_relations(evt);
/* hb */
for(const IID<int> &b_iid : evt.cur_param.ER.EHB.after_I){
for(const IID<int> &a_iid : evt.cur_param.ER.EHB.I){
Event &a = get_evt(a_iid);
Event &b = get_evt(b_iid);
assert(a.committed && b.committed);
a.rel.hb.fwd.insert(b_iid);
b.rel.hb.bwd.insert(a_iid);
}
}
for(const IID<int> &b_iid : evt.cur_param.ER.EHB.after_C){
for(const IID<int> &a_iid : evt.cur_param.ER.EHB.C){
Event &a = get_evt(a_iid);
Event &b = get_evt(b_iid);
assert(a.committed && b.committed);
a.rel.hb.fwd.insert(b_iid);
b.rel.hb.bwd.insert(a_iid);
}
}
/* prop */
for(auto pr : evt.cur_param.ER.prop){
const IID<int> &a_iid = pr.first;
for(const IID<int> &b_iid : pr.second){
Event &a = get_evt(a_iid);
Event &b = get_evt(b_iid);
assert(a.committed && b.committed);
a.rel.prop.fwd.insert(b_iid);
b.rel.prop.bwd.insert(a_iid);
}
}
/* cb */
evt.cb_bwd = compute_cb(evt);
}
template<MemoryModel MemMod,CB_T CB,class Event>
BVClock TB<MemMod,CB,Event>::compute_cb(const Event &evt, bool include_rf){
BVClock cb;
cb.set(evt.clock_index);
const int proc = evt.iid.get_pid();
for(int i : evt.addr_deps) cb += fch[proc][i-1].cb_bwd;
for(int i : evt.data_deps) cb += fch[proc][i-1].cb_bwd;
for(int i : evt.ctrl_deps) cb += fch[proc][i-1].cb_bwd;
for(int i : evt.ctrl_isync_deps) cb += fch[proc][i-1].cb_bwd; // Capture the ctrl deps which are also ctrl+isync deps
if(include_rf){
for(const IID<int> &iid : evt.rel.rf.bwd){
cb += get_evt(iid).cb_bwd;
}
}
if(CB == CB_ARM || CB == CB_POWER){
/* addr;po U lwsync U sync */
const int snc = std::max(evt.lwsync_idx_before, evt.sync_idx_before);
for(int i = evt.iid.get_index()-2; 0 <= i; --i){
if(i < snc){ // before a lwsync or sync
cb += fch[proc][i].cb_bwd;
if(fch[proc][i].lwsync_idx_before == i ||
fch[proc][i].sync_idx_before == i){
/* All earlier events are already covered by fch[proc][i].cb_bwd */
break;
}
}else{ // addr;po
for(int j : fch[proc][i].addr_deps){
cb += fch[proc][j-1].cb_bwd;
}
}
}
}
if(CB == CB_POWER){
/* po-loc */
for(const IID<int> &iid : evt.rel.poloc.bwd){
cb += get_evt(iid).cb_bwd;
}
}
return cb;
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::return_relations(Event &evt){
for(const IID<int> &iid : evt.rel.rf.fwd){
get_evt(iid).rel.rf.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.rf.bwd){
get_evt(iid).rel.rf.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.co.fwd){
get_evt(iid).rel.co.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.co.bwd){
get_evt(iid).rel.co.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.com.fwd){
get_evt(iid).rel.com.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.com.bwd){
get_evt(iid).rel.com.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.poloc.fwd){
get_evt(iid).rel.poloc.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.poloc.bwd){
get_evt(iid).rel.poloc.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.ii0.fwd){
get_evt(iid).rel.ii0.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.ii0.bwd){
get_evt(iid).rel.ii0.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.ci0.fwd){
get_evt(iid).rel.ci0.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.ci0.bwd){
get_evt(iid).rel.ci0.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.cc0.fwd){
get_evt(iid).rel.cc0.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.cc0.bwd){
get_evt(iid).rel.cc0.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.hb.fwd){
get_evt(iid).rel.hb.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.hb.bwd){
get_evt(iid).rel.hb.fwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.prop.fwd){
get_evt(iid).rel.prop.bwd.insert(evt.iid);
}
for(const IID<int> &iid : evt.rel.prop.bwd){
get_evt(iid).rel.prop.fwd.insert(evt.iid);
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void Mem<MemMod,CB,Event>::commit(Event &evt, const ByteAccess &A, const Param::Choice &C){
if(A.type == ByteAccess::STORE){
coherence.push_back(evt.iid);
loads.emplace_back();
for(int i = int(coherence.size())-1; C.co_pos < i; --i){
coherence[i] = coherence[i-1];
loads[i+1] = loads[i];
}
coherence[C.co_pos] = evt.iid;
loads[C.co_pos+1].clear();
}else{ // A.type == ByteAccess::LOAD
assert(loads.size() == coherence.size() + 1);
if(C.src.is_null()){
loads[0].insert(evt.iid);
}else{
int l = 1;
while(coherence[l-1] != C.src) ++l; // Find the source store's position
loads[l].insert(evt.iid);
}
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::get_cur_load_values(Event &evt, std::vector<MBlock> *values){
get_load_values(evt,values,evt.cur_param);
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::get_load_values(Event &evt, std::vector<MBlock> *values, const Param &B){
values->clear();
for(int i = 0; i < evt.load_count; ++i){
values->push_back(MBlock(evt.accesses[i].addr,evt.accesses[i].addr.size));
char *block = (char*)values->back().get_block();
for(int j = 0; j < evt.accesses[i].addr.size; ++j){
void *p = (void*)&((char*)evt.accesses[i].addr.ref)[j];
int k;
/* Find the byte load access of p */
for(k = 0; !(evt.baccesses[k].addr == p && evt.baccesses[k].type == ByteAccess::LOAD); ++k) ;
if(B.choices[k].src.is_null()){ // Initial value
block[j] = *(char*)p; // Get the value directly from memory
}else{ // Get value from source store event
Event &wevt = get_evt(B.choices[k].src);
for(const ByteAccess &A : wevt.baccesses){
if(A.addr == p &&
A.type == ByteAccess::STORE){
block[j] = A.data;
break;
}
}
}
}
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::detect_rw_conflicts(Event &w_evt){
const int proc = w_evt.iid.get_pid();
const int idx = w_evt.iid.get_index();
std::function<bool(Event&)> is_mutex_lock =
[](Event &e){
return e.baccesses.size() == 2 &&
e.accesses.size() == 2 &&
e.load_count == 1 &&
e.baccesses[0].addr == e.baccesses[1].addr &&
e.accesses[0].load_req;
};
VecSet<IID<int> > conflicts;
bool w_is_mutex_lock = is_mutex_lock(w_evt);
BVClock cb_wo_rf; // cb relation excluding incoming rf-edges to w_evt
if(w_is_mutex_lock){
cb_wo_rf = compute_cb(w_evt,false);
}
for(const ByteAccess &A : w_evt.baccesses){
if(A.type == ByteAccess::LOAD) continue;
Mem<MemMod,CB,Event> &m = mem[A.addr];
for(unsigned i = 0; i < m.loads.size(); ++i){
for(const IID<int> &riid : m.loads[i]){
Event &r_evt = get_evt(riid);
if(riid.get_pid() == proc && riid.get_index() <= idx) continue; // w_evt cannot be the source
if(w_is_mutex_lock && is_mutex_lock(r_evt)){
/* Special treatment for lock -> lock conflicts. */
if(0 <= r_evt.branch_end && prefix[r_evt.branch_end] != r_evt.iid) continue;
if(0 <= r_evt.branch_end) continue; // NOTICE: Is this check correct?
if(cb_wo_rf[r_evt.clock_index]) continue;
conflicts.insert(riid);
}else{
if(w_evt.cb_bwd[r_evt.clock_index]) continue;
if(0 <= r_evt.branch_end && prefix[r_evt.branch_end] != r_evt.iid) continue;
conflicts.insert(riid);
}
}
}
}
VecSet<void*> w_stbytes;
for(const ByteAccess &A : w_evt.baccesses){
w_stbytes.insert(A.addr);
}
for(const IID<int> &riid : conflicts){
Branch bnc;
Event &r_evt = get_evt(riid);
const bool lock_lock_race = w_is_mutex_lock && is_mutex_lock(r_evt);
int bnc_start;
if(0 <= r_evt.branch_start){
bnc_start = r_evt.branch_start;
}else{
bnc_start = 0;
while(prefix[bnc_start] != riid) ++bnc_start;
}
VecSet<IID<int> > removed;
std::function<void(const Event&,Param&)> decrease_co_pos =
[&removed,this](const Event &evt, Param &P){
/* Decrease coherence positions corresponding to the number
* of removed co-earlier stores. */
for(unsigned b = 0; b < evt.baccesses.size(); ++b){
const ByteAccess &B = evt.baccesses[b];
if(B.type == ByteAccess::STORE){
Mem<MemMod,CB,Event> &m = this->mem[B.addr];
for(unsigned j = 0; m.coherence[j] != evt.iid; ++j){
if(removed.count(m.coherence[j])){
assert(P.choices[b].is_coherence_choice());
--P.choices[b].co_pos;
}
}
}
}
};
for(int i = bnc_start; i < sched_count; ++i){
Event &ievt = get_evt(prefix[i]);
if((!lock_lock_race && w_evt.cb_bwd[ievt.clock_index]) ||
(lock_lock_race && cb_wo_rf[ievt.clock_index])){
Param P;
P.choices = ievt.cur_param.choices;
decrease_co_pos(ievt,P);
bnc.branch.push_back({prefix[i],P});
}else if(ievt.has_store){
removed.insert(prefix[i]);
}
}
if(lock_lock_race){ // Special treatment for lock->lock races
Param P;
bnc.branch.push_back({w_evt.iid,P});
bnc.param_type = Branch::PARAM_STAR;
}else{
/* Add the store event w_evt.iid and the load event riid to the
* end of the branch. Give them dummy parameters. They are going
* to have their parameters recalculated anyway according to
* PAEvent::RECALC_STAR and PAEvent::RECALC_LOAD respectively.
*/
Param P;
bnc.branch.push_back({w_evt.iid,P});
bnc.branch.push_back({riid,P});
bnc.param_type = Branch::PARAM_WR;
}
normalise_branch(bnc);
assert(get_evt(prefix[bnc_start]).branch_start < 0 || get_evt(prefix[bnc_start]).cur_branch.branch.size());
if(get_evt(prefix[bnc_start]).branch_start < 0 || get_evt(prefix[bnc_start]).cur_branch < bnc){
assert(get_evt(prefix[bnc_start]).branch_start < 0 || get_evt(prefix[bnc_start]).branch_start == bnc_start);
get_evt(prefix[bnc_start]).new_branches.insert(bnc);
}
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::normalise_branch(Branch &B){
/* Use insertion sort to order all events in B, except for the
* suffix of B which is fixed (the store and the load in case of
* R->W, or the lock in case of lock->lock).
*
* The order according to which the events are sorted is cb, where
* ties are broken by comparing IID.
*/
std::function<bool(const Branch::PEvent&,const Branch::PEvent&)> lt = // Comparison function
[this](const Branch::PEvent &A, const Branch::PEvent &B){
const Event &e0 = this->get_evt(A.iid);
const Event &e1 = this->get_evt(B.iid);
if(e1.cb_bwd[e0.clock_index]) return true;
assert(!e0.cb_bwd[e1.clock_index]); // In normalise_branch A and B should never be compared when B-cb->A.
return A.iid < B.iid;
};
int last_event = -1;
switch(B.param_type){
case Branch::PARAM_WR:
last_event = int(B.branch.size())-2;
break;
case Branch::PARAM_STAR:
last_event = int(B.branch.size())-1;
break;
default:
throw std::logic_error("POWERARMTraceBuilder::normalise_branch: Unknown type of branch.");
}
for(int i = 1; i < last_event; ++i){
int j = i;
while(0<j && !lt(B.branch[j-1],B.branch[j])){
/* Switch B.branch[j-1] and B.branch[j]
*
* If B.branch[j-1] and B.branch[j] store to the same byte,
* also nudge their coherence positions.
*/
Event &e0 = get_evt(B.branch[j-1].iid);
Event &e1 = get_evt(B.branch[j].iid);
for(unsigned a = 0; a < e0.baccesses.size(); ++a){
if(e0.baccesses[a].type != ByteAccess::STORE) continue;
for(unsigned b = 0; b < e1.baccesses.size(); ++b){
if(e1.baccesses[b].type != ByteAccess::STORE) continue;
if(e0.baccesses[a].addr == e1.baccesses[b].addr){
if(B.branch[j-1].param.choices[a].co_pos < B.branch[j].param.choices[b].co_pos){
--B.branch[j].param.choices[b].co_pos;
}else{
++B.branch[j-1].param.choices[a].co_pos;
}
}
}
}
Branch::PEvent tmp = std::move(B.branch[j]);
B.branch[j] = std::move(B.branch[j-1]);
B.branch[j-1] = std::move(tmp);
--j;
}
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::populate_parameters(Event &evt){
const int proc = evt.iid.get_pid();
const int idx = evt.iid.get_index();
assert(evt.new_params.empty());
std::vector<Param> prm, next_prm;
prm.emplace_back(); // Empty parameter to start with
Param &B0 = prm.back();
fences_to_hb(evt,B0.rel.hb);
for(int i : evt.addr_deps){
B0.rel.ii0.bwd.insert(IID<int>(proc,i));
B0.rel.cc0.bwd.insert(IID<int>(proc,i));
}
for(int i : evt.data_deps){
B0.rel.ii0.bwd.insert(IID<int>(proc,i));
B0.rel.cc0.bwd.insert(IID<int>(proc,i));
}
for(int i : evt.ctrl_deps){
B0.rel.cc0.bwd.insert(IID<int>(proc,i));
}
for(int i : evt.ctrl_isync_deps){
B0.rel.ci0.bwd.insert(IID<int>(proc,i));
}
for(int i = 0; i < idx-1; ++i){
for(int j : fch[proc][i].addr_deps){
if(fch[proc][j-1].committed){
B0.rel.cc0.bwd.insert(IID<int>(proc,i)); // addr;po
}
}
}
for(int i = idx; i < threads[proc].fch_count; ++i){
if(fch[proc][i].addr_deps.count(idx)){
/* All later events are addr;po-after this event. */
for(int j = i+1; j < threads[proc].fch_count; ++j){
if(fch[proc][j].committed){
B0.rel.cc0.fwd.insert(IID<int>(proc,j+1)); // addr;po
}
}
break;
}
}
for(unsigned bi = 0; bi < evt.baccesses.size(); ++bi){
const ByteAccess &BA = evt.baccesses[bi];
for(const Param &B : prm){
if(BA.type == ByteAccess::STORE){
populate_parameters_store(evt,bi,BA,B,next_prm);
}else{ // BA.type == ByteAccess::LOAD
populate_parameters_load(evt,bi,BA,B,next_prm);
}
}
/* Let prm and next_prm switch roles */
prm.swap(next_prm);
next_prm.clear();
}
bool has_load_req = false;
for(const Access &A : evt.accesses){
if(A.load_req){
has_load_req = true;
break;
}
}
/* Check the parameters against the axioms NO THIN AIR,
* OBSERVATION and PROPAGATION. Inserts the allowed parameters
* into new_params. */
evt.new_params.reserve(prm.size());
for(unsigned i = 0; i < prm.size(); ++i){
Param B = prm[i];
ppo_to_hb(evt,B.rel,B.ER.EHB);
if(CB == CB_POWER){
/* hb subseteq cb_POWER, so there can be no cycles. */
assert(no_thin_air(evt,B.rel,B.ER.EHB));
}else{
if(!no_thin_air(evt,B.rel,B.ER.EHB)) continue;
}
calc_prop(evt,B.rel,B.ER);
if(!propagation(evt,B.rel,B.ER)) continue;
if(!observation(evt,B.rel,B.ER.EHB)) continue;
bool ok_load_reqs = true;
if(has_load_req){
std::vector<MBlock> values;
get_load_values(evt,&values,B);
for(int i = 0; i < evt.load_count; ++i){
if(evt.accesses[i].load_req && !(*evt.accesses[i].load_req)(values[i])){
ok_load_reqs = false;
break;
}
}
}
if(!ok_load_reqs) continue;
evt.new_params.push_back(B);
}
}
template<MemoryModel MemMod,CB_T CB,class Event>
void TB<MemMod,CB,Event>::populate_parameters_store(Event &evt,int stidx,const ByteAccess &S,
const Param &B,std::vector<Param> ¶meters){
const int proc = evt.iid.get_pid();
Mem<MemMod,CB,Event> &m = mem[S.addr];
/* Compute the allowed coherence positions for the store access.
*
* This will be done by gradually narrowing a range of possible
* positions between (and including) first and last.
*/
int first = 0, last = int(m.coherence.size());
Rel poloc = B.rel.poloc;
Rel cc0 = B.rel.cc0;
/**************************
* AXIOM: SC PER LOCATION *
**************************/
{
IID<int> poloc_before_iid, poloc_after_iid;
int poloc_before_idx, poloc_after_idx;
ByteAccess::Type poloc_before_tp, poloc_after_tp;
find_poloc(evt,m,poloc_before_iid,poloc_before_idx,poloc_before_tp,
poloc_after_iid,poloc_after_idx,poloc_after_tp);
if(!poloc_before_iid.is_null()){
if(MemMod == POWER) cc0.bwd.insert(poloc_before_iid);
poloc.bwd.insert(poloc_before_iid);
if(poloc_before_tp == ByteAccess::STORE){
first = poloc_before_idx+1;
}else{
first = poloc_before_idx;
}
}
if(!poloc_after_iid.is_null()){
if(MemMod == POWER) cc0.fwd.insert(poloc_after_iid);
poloc.fwd.insert(poloc_after_iid);
if(poloc_after_tp == ByteAccess::STORE){
last = poloc_after_idx;
}else{
last = poloc_after_idx-1;
}
}
clear_event_colour();
com_poloc_bwd_search(B.rel.com.bwd,{});
com_poloc_bwd_search(B.rel.poloc.bwd,{});
/* Check which events we are already com-poloc-after */
for(int i = m.coherence.size()-1; first <= i; --i){ // Check stores
if(get_evt(m.coherence[i]).colour){
first = i+1;
break;
}
}
for(int i = m.loads.size()-1; first < i; --i){ // Check loads
for(const IID<int> &liid : m.loads[i]){
if(get_evt(liid).colour){
first = i;
}
}
}
/* Check which events we cannot be after */
VecSet<IID<int> > compoloc_after(B.rel.com.fwd);
compoloc_after.insert(B.rel.poloc.fwd);
for(int i = first; i <= last; ++i){
if((0 < i && // Check store
com_poloc_bwd_search({m.coherence[i-1]},compoloc_after))
||
(com_poloc_bwd_search(m.loads[i],compoloc_after))){
last = i-1;
}
}