VHDL: Compile error while assigning attributes to "all" signals.

[aqeelmahroof]

Hi Nick,

I having compilation issues while assigning attributes to all signals using the keyword all.
code (attached here mark_debug_issue.zip)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mark_debug_all is
  generic(
    G_MORE_DELAY    : boolean := true
  );  
  port (
    clk                        : in  std_logic; 
    din                        : in  std_logic_vector(4-1 downto 0);
    dout                       : out std_logic_vector(4-1 downto 0)
  );
  end mark_debug_all;

  architecture rtl of mark_debug_all is
  
    signal z1            : std_logic_vector(4-1 downto 0);
    signal z2            : std_logic_vector(4-1 downto 0);
    attribute mark_debug : string;
    attribute mark_debug of all : signal is "True"; -------------------------------------- * 
    
  begin
  
    p_delay: process(clk)
    begin
       if (rising_edge(clk)) then
        z1 <= din;
        z2 <= z1 ;
      end if;
    end process;
  
    -- dummy process 
    gen_more_delay : if G_MORE_DELAY generate
      signal z3            : std_logic_vector(4-1 downto 0);
      signal z4            : std_logic_vector(4-1 downto 0); 
      attribute mark_debug of all : signal is "True"; -------------------------------------- * 
    begin
      p_delay: process(clk)
      begin
         if (rising_edge(clk)) then
          z3 <= z2;
          z4 <= z3;
          dout <= z4;
        end if;
      end process;
    end generate gen_more_delay;
    
    gen_no_delay : if not G_MORE_DELAY generate
    begin
      dout <= z2;
    end generate gen_no_delay;

  end architecture rtl;

to run

nvc --std=93 -a ./mark_debug_all.vhd

nvc version :- nvc 1.13-devel (1.12.0.r41.g3edb4fec) (Using LLVM 14.0.0)

Note:- This works fine whith Questa.