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The recent improvements came from profiling a design a user shared with with me privately. If anyone has large designs either public or private that they can share with me I'm happy to take a look. I've got some ideas for improving how drivers are represented that would reduce overhead, but most concrete performance improvements come from fixing an issue found in some particular benchmark. |
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OK, I see thanks. Do you think it would be worth-it to expose the profiler of the generated code to the user ? So that user can see which code takes the longest to simulate? |
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Hi @nickg , I have noticed you have optimized many things, including IEEE std_logic operations.
Profiling the latest master vs 1.10 release gives me about 20-23 % simulation speedup.
I was wondering whether you plan to do any further optimizations, or whether you are aware
of any other potential sweet-spots for performance optimizations.
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