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Issue to track the development of a chip-level tests for either pre-silicon and post-silicon environments.
Component:ChipLevelTest
Test point name with link to entry in test plan.
Does this test require development of a host side component? (In other words, does the test require an external stimulus, like receiving UART or SPI transactions?)
Does the required opentitantool infrastructure exist so that the Rust component can be developed? If not, this must be developed in SV. 'None' means that there is no Rust component for this test.
Does the test need to run in SiVal targets? If the answer is yes, the test will required to be enabled in the relevant FPGA target platform. Add the "Component:SiliconValidation" after creating the issue.
GitHub username for a hardware engineer who can answer questions.