{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":204516692,"defaultBranch":"master","name":"opentitan","ownerLogin":"lowRISC","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2019-08-26T16:30:16.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/7814611?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1714804720.0","currentOid":""},"activityList":{"items":[{"before":"0ad819b1bd207299cda3cf6f519e5dee0dab8569","after":"d0c52cdadd94271b76969f8a89f88c98d63273c9","ref":"refs/heads/master","pushedAt":"2024-05-04T23:51:30.000Z","pushType":"pr_merge","commitsCount":7,"pusher":{"login":"timothytrippel","name":"Timothy Trippel","path":"/timothytrippel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5633066?s=80&v=4"},"commit":{"message":"[personalization] add comparing certificate hashes\n\nCalculate combined certificates' hashes on the host before sending\nthem to the device, and on the device after retrieving them from the\nflash storage, and compare the resutling hashes.\n\nTested on the FPGA setup by successfully running\n bazel run //sw/host/opentitantool -- --interface=hyper310 fpga \\\n clear-bitstream && \\\n bazel test --test_output=streamed \\\n //sw/device/silicon_creator/manuf/skus/earlgrey_a0/sival_bringup:ft_provision_fpga_cw310_sival\n\nSigned-off-by: Vadim Bendebury ","shortMessageHtmlLink":"[personalization] add comparing certificate hashes"}},{"before":"49d4e53c1beb1124beab2b35138a2bfda98af827","after":"0ad819b1bd207299cda3cf6f519e5dee0dab8569","ref":"refs/heads/master","pushedAt":"2024-05-04T06:47:15.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jesultra","name":null,"path":"/jesultra","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/15022811?s=80&v=4"},"commit":{"message":"[rom] Avoid touching watchdog config on wake from sleep\n\nWhen waking from sleep, the watchdog IP will not have been reset, so it\nis not necessary to re-configure it. In fact, if watchdog REGWEN has\nbeen used to disable writes to its registers, attempting to do so can\ngenerate an exception causing chip reset, which will reset not only the\nwatchdog, but other IP blocks that the owner code wanted retained across\nthe period of sleep.\n\nAlso, do not re-configure pinmux or attempt to read SW_BOOTSTRAP pins if\nwaking from sleep.\n\nSigned-off-by: Jes B. Klinke \nChange-Id: I503fd65f2203c425ae01ea7044479533aeac8895","shortMessageHtmlLink":"[rom] Avoid touching watchdog config on wake from sleep"}},{"before":"5fc98074d1d42d88a97765d2d7e5f53166451f7e","after":"8be5cf2908fed73dccd030920ca4727efc2b1c1f","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-04T06:41:30.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"engdoreis","name":"Douglas Reis","path":"/engdoreis","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/65042207?s=80&v=4"},"commit":{"message":"[sival, spi] Link spi_passthru to testplan\n\nSigned-off-by: Douglas Reis ","shortMessageHtmlLink":"[sival, spi] Link spi_passthru to testplan"}},{"before":"38a428a0bfd175e06fbccf04b8b5c7e5e8f1526e","after":"5fc98074d1d42d88a97765d2d7e5f53166451f7e","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-04T06:00:26.000Z","pushType":"pr_merge","commitsCount":6,"pusher":{"login":"timothytrippel","name":"Timothy Trippel","path":"/timothytrippel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5633066?s=80&v=4"},"commit":{"message":"[dice] refactor dice lib to reduce code size\n\nThis refactors the dice lib to optimize code reuse and follow lib asset\nnaming conventions.\n\nSigned-off-by: Tim Trippel \n(cherry picked from commit b217f41a378e30cdef6685c1d26fb3e990db0b4e)","shortMessageHtmlLink":"[dice] refactor dice lib to reduce code size"}},{"before":"f9b341f4ac57a12a08821843cdc1a4a1eec249d3","after":"49d4e53c1beb1124beab2b35138a2bfda98af827","ref":"refs/heads/master","pushedAt":"2024-05-04T05:09:42.000Z","pushType":"pr_merge","commitsCount":8,"pusher":{"login":"andreaskurth","name":"Andreas Kurth","path":"/andreaskurth","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3583291?s=80&v=4"},"commit":{"message":"[keymgr/rtl] Raise error for any operation in Invalid state\n\nThe keymgr specification states that no operation is allowed in the\nInvalid state. Prior to this commit, keymgr did not raise an *invalid\noperation* error, raise an alert, nor update the `OP_STATUS` and\n`ERR_CODE` CSRs.\n\nThis commit fixes keymgr to do all these things.\n\nSigned-off-by: Andreas Kurth ","shortMessageHtmlLink":"[keymgr/rtl] Raise error for any operation in Invalid state"}},{"before":"ad79631e8b50d35770cd6201a3bbd38f588fe07a","after":"38a428a0bfd175e06fbccf04b8b5c7e5e8f1526e","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-04T04:40:16.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"moidx","name":"moidx","path":"/moidx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/4177786?s=80&v=4"},"commit":{"message":"[rom_ext] Relax EDN0 configuration.\n\nThis change aims to mitigate some of the side effects caused by\n\n1. Increase the reseed interval in EDN0 to reduce the number of requests\n going to entropy_src.\n2. Increase the reseed interval in keymgr to reduce the number of\n requests going to edn0.\n\nBoth configuration values will be updated later on based on\nrecommendations derived from penetration testing and pre-silicon\nevaluation.\n\nThis change is was adapted from lowRISC/opentitan#22944.\n\nSigned-off-by: Miguel Osorio ","shortMessageHtmlLink":"[rom_ext] Relax EDN0 configuration."}},{"before":"e2eff209029822f857d13f25dc37734cbe8b32c9","after":"f9b341f4ac57a12a08821843cdc1a4a1eec249d3","ref":"refs/heads/master","pushedAt":"2024-05-04T03:39:03.000Z","pushType":"pr_merge","commitsCount":7,"pusher":{"login":"a-will","name":"Alex Williams","path":"/a-will","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/782139?s=80&v=4"},"commit":{"message":"[i2c,dif] Add DIFs for the bus monitor features\n\nAdd the ability to enable the multi-controller mode of the bus monitor.\n\nChange the DIFs for the clock stretching timeout enablement to allow\nselecting between that and the bus timeout, just like the hardware.\n\nFix up tests to match the new APIs.\n\nSigned-off-by: Alexander Williams ","shortMessageHtmlLink":"[i2c,dif] Add DIFs for the bus monitor features"}},{"before":"6d494544f58403e78f858685379aecc3917a8e7f","after":"ad79631e8b50d35770cd6201a3bbd38f588fe07a","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-03T23:49:09.000Z","pushType":"pr_merge","commitsCount":4,"pusher":{"login":"timothytrippel","name":"Timothy Trippel","path":"/timothytrippel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5633066?s=80&v=4"},"commit":{"message":"[ot_certs] Replace unsafe code with safe wrapper\n\nThe newer version of the openssl crate provides a safe wrapper\nto get a directory name out of a general name.\n\nSigned-off-by: Amaury Pouly \n(cherry picked from commit 16a55f086879dc692646de3e6fe391f878d69c8f)","shortMessageHtmlLink":"[ot_certs] Replace unsafe code with safe wrapper"}},{"before":"911fc044bfea2624e25847608b0621284ab1e309","after":"6d494544f58403e78f858685379aecc3917a8e7f","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-03T19:54:20.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"timothytrippel","name":"Timothy Trippel","path":"/timothytrippel","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5633066?s=80&v=4"},"commit":{"message":"[rom_ext] temporarily disable cert updating\n\nThis temporarily disables DICE certificate updating in the ROM_EXT to\nunblock CI. A more permanent fix to #22921 will be rolled out shortly.\n\nSigned-off-by: Tim Trippel \n(cherry picked from commit 9632f15f745f96700e0866241860289c7c0aaed6)","shortMessageHtmlLink":"[rom_ext] temporarily disable cert updating"}},{"before":"d3a703e9b64626f046c21adfb89053ab9b866420","after":"911fc044bfea2624e25847608b0621284ab1e309","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-03T19:08:47.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"cfrantz","name":null,"path":"/cfrantz","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/628742?s=80&v=4"},"commit":{"message":"[rom_ext] Advance the security version in boot_data\n\n1. When the security version of the just-booted ROM_EXT is greater than\n the ROM_EXT minimum security version in boot data, move the value\n forward.\n2. Provide a mechanism in the manifest to prevent moving foward even\n though the version is newer. This is to release test ROM_EXTs\n without running afoul of #22941.\n\nThis should NOT be cherry-picked to master. We will fix this on master\nby adjusting the selection criteria as discussed in #22941.\n\nSigned-off-by: Chris Frantz ","shortMessageHtmlLink":"[rom_ext] Advance the security version in boot_data"}},{"before":"36953225b612e0adb44c10037500160eda097f87","after":"e2eff209029822f857d13f25dc37734cbe8b32c9","ref":"refs/heads/master","pushedAt":"2024-05-03T18:33:31.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"andreaskurth","name":"Andreas Kurth","path":"/andreaskurth","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3583291?s=80&v=4"},"commit":{"message":"[hmac,dv] Extend DV to test invalid configurations\n\nSigned-off-by: Ghada Dessouky ","shortMessageHtmlLink":"[hmac,dv] Extend DV to test invalid configurations"}},{"before":"89204128efb5ff9e1c29570b999b27c3a90756f5","after":"d3a703e9b64626f046c21adfb89053ab9b866420","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-03T17:07:06.000Z","pushType":"pr_merge","commitsCount":6,"pusher":{"login":"jwnrt","name":"James Wainwright","path":"/jwnrt","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/105280833?s=80&v=4"},"commit":{"message":"[sival] Link scrambled access test to testplan\n\nSigned-off-by: James Wainwright \n(cherry picked from commit 32696631be6857d66b5baa66d88e7cbbb86dde01)","shortMessageHtmlLink":"[sival] Link scrambled access test to testplan"}},{"before":"854377469faad0f02138d2cdacdf36988f1bcf03","after":"36953225b612e0adb44c10037500160eda097f87","ref":"refs/heads/master","pushedAt":"2024-05-03T17:05:55.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jwnrt","name":"James Wainwright","path":"/jwnrt","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/105280833?s=80&v=4"},"commit":{"message":"[sival,pwrmgr] Lift pwrmgr_usbdev_smoketest out of sim_dv and enable sival\n\nSigned-off-by: James Wainwright ","shortMessageHtmlLink":"[sival,pwrmgr] Lift pwrmgr_usbdev_smoketest out of sim_dv and enable …"}},{"before":"74b3a45bebf97973788372dfbd1efac120a94c6c","after":"854377469faad0f02138d2cdacdf36988f1bcf03","ref":"refs/heads/master","pushedAt":"2024-05-03T16:00:40.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"a-will","name":"Alex Williams","path":"/a-will","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/782139?s=80&v=4"},"commit":{"message":"[spi_device] Track intercept_en along the read pipeline\n\nintercept_en is used to select between the passthrough and internal read\npaths, but when the fast read pipeline is enabled, this selector needs\nto follow the data values that it is meant to select. Add intercept_en\nto the set of signals that pass through the read pipeline, so the\ncorrect data can be selected on the cycle in which it is used.\n\nWithout this change, transitions from the mailbox to passthrough may\ncause passthrough data to appear when the last mailbox data should be\ntransmitted.\n\nSigned-off-by: Alexander Williams ","shortMessageHtmlLink":"[spi_device] Track intercept_en along the read pipeline"}},{"before":"15828a605d45e46a62676307c224718b77d49cb8","after":"74b3a45bebf97973788372dfbd1efac120a94c6c","ref":"refs/heads/master","pushedAt":"2024-05-03T11:15:09.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"rswarbrick","name":"Rupert Swarbrick","path":"/rswarbrick","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/104845?s=80&v=4"},"commit":{"message":"[alert_handler,dv] Disable an assertion that breaks for FI tests\n\nThis assertion was moved from an FPV file to the design itself in\ncommit a4ad7a84c9b. The assertion is true (it's even provable!) in an\nFPV setting, but isn't true if you start forcing variables. Disable it\nfor FI tests accordingly.\n\nSigned-off-by: Rupert Swarbrick ","shortMessageHtmlLink":"[alert_handler,dv] Disable an assertion that breaks for FI tests"}},{"before":"092400ac012b7091c22b45ef5e9a5ac5d12b9845","after":"15828a605d45e46a62676307c224718b77d49cb8","ref":"refs/heads/master","pushedAt":"2024-05-03T10:43:54.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"jwnrt","name":"James Wainwright","path":"/jwnrt","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/105280833?s=80&v=4"},"commit":{"message":"[sival] Fix bazel tags for random sleep test\n\nSigned-off-by: James Wainwright ","shortMessageHtmlLink":"[sival] Fix bazel tags for random sleep test"}},{"before":"a4d9f164bb7495a5c4275c8b2094fd86f45a2e8c","after":"092400ac012b7091c22b45ef5e9a5ac5d12b9845","ref":"refs/heads/master","pushedAt":"2024-05-03T09:59:23.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"vogelpi","name":"Pirmin Vogel","path":"/vogelpi","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20307557?s=80&v=4"},"commit":{"message":"[rv_core_ibex] Reduce number of PRINCE rounds in ICache for timing\n\nTo improve timing, this commit reduces the number of half rounds of the\nPRINCE cipher used for ICache scrambling from 3 (7 effective rounds)\nback to 2 (5 effective rounds). All other scrambled memory primitives\nin the design keep using 3 half rounds (7 effective rounds). For the\nICache, we have less stringent security requirements and a weaker\nscrambling is acceptable.\n\nSigned-off-by: Pirmin Vogel ","shortMessageHtmlLink":"[rv_core_ibex] Reduce number of PRINCE rounds in ICache for timing"}},{"before":"7f3ce9509abf7965f21a86224813dde6b741ac74","after":"89204128efb5ff9e1c29570b999b27c3a90756f5","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-03T09:51:31.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"engdoreis","name":"Douglas Reis","path":"/engdoreis","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/65042207?s=80&v=4"},"commit":{"message":"[sival,pwrmgr] Lift pwrmgr_usbdev_smoketest out of sim_dv and enable sival\n\nSigned-off-by: James Wainwright ","shortMessageHtmlLink":"[sival,pwrmgr] Lift pwrmgr_usbdev_smoketest out of sim_dv and enable …"}},{"before":"5dbbd252ce8531680fde18361614ed07c783b5c7","after":"a4d9f164bb7495a5c4275c8b2094fd86f45a2e8c","ref":"refs/heads/master","pushedAt":"2024-05-03T09:19:21.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"vogelpi","name":"Pirmin Vogel","path":"/vogelpi","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20307557?s=80&v=4"},"commit":{"message":"[otbn] Detect unexpected partial \"secure\" wipes\n\nThis commit adds a little bit of security hardening around signals used\nfor zeroing parts of the OTBN state during secure wipe. To this end, the\nsecure_wipe_running_o signal is registered inside the start stop\ncontroller (to get distinct driving cells) and the critical signals\nare compared against the secure_wipe_running signal at the point of\nconsumption.\n\nThis resolves lowRISC/OpenTitan#12061.\n\nCo-authored-by: Greg Chadwick \nSigned-off-by: Pirmin Vogel ","shortMessageHtmlLink":"[otbn] Detect unexpected partial \"secure\" wipes"}},{"before":"96f07933915ac697935502d280df10ff439504a3","after":"5dbbd252ce8531680fde18361614ed07c783b5c7","ref":"refs/heads/master","pushedAt":"2024-05-03T07:10:29.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jadephilipoom","name":null,"path":"/jadephilipoom","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/6509194?s=80&v=4"},"commit":{"message":"[rom] Change the size of the key pair field in SPHINCS+ addresses.\n\nThis change does not affect the sphincsplus-shake-128s parameter set we\nuse, since the key pair field is less than two bytes for all of the\nparameter sets that were submitted to the NIST competition. However,\nsome choices of parameters need a larger field, so for maximum\nflexibility it makes sense to adjust. This change does not have any\nsignificant effect on performance, since these copies/writes are not on\nthe hot path (checked this locally as well).\n\nCorresponds to commit 7ec789a from the SPHINCS+ reference\nimplementation (PR 60):\nhttps://github.com/sphincs/sphincsplus/commit/7ec789ace6874d875f4bb84cb61b81155398167e\n\nSigned-off-by: Jade Philipoom ","shortMessageHtmlLink":"[rom] Change the size of the key pair field in SPHINCS+ addresses."}},{"before":"c7f7b8a766901d36555bfd41e22a8e5f7829d566","after":"96f07933915ac697935502d280df10ff439504a3","ref":"refs/heads/master","pushedAt":"2024-05-03T05:34:50.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"moidx","name":"moidx","path":"/moidx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/4177786?s=80&v=4"},"commit":{"message":"[rom] Remove real and fake key targets.\n\nNow that ROM keys have moved to OTP, there is no longer a need for\nmaintaining fake and real keys rom targets. The execution environments\nshould be able to handle the key configuration based on the OTP profile.\nThis change contains the following updates:\n\n1. Introduce the //sw/silicon_creator/rom/mask_rom target, replacing the\n rom_with_fake_keys and rom_with_real_keys targets. Update all\n dependencies previously consuming the old targets.\n2. Reduce the number of bitstreams to only support OTP configurations\n with either `test_rom` and `mask_rom`. All changes are reflected in\n //hw/bitstreams and consuming targets.\n3. Update DV targets to use a single mask_rom target. This is to ensure\n it is clear in the DV target configuration which ROM target is being\n used, without making any claims on the OTP configuration.\n4. Leave all other FPGA targets as is. For example\n fpga_cw310_rom_with_fake_keys after this change means that the\n bitstream has been configured with the new mask_rom target as well as\n an OTP image containing fake signing keys.\n\nSigned-off-by: Miguel Osorio ","shortMessageHtmlLink":"[rom] Remove real and fake key targets."}},{"before":"930c0cc9144c29c69a371bdb9c30ad33b5c42bf3","after":"c7f7b8a766901d36555bfd41e22a8e5f7829d566","ref":"refs/heads/master","pushedAt":"2024-05-03T05:34:17.000Z","pushType":"pr_merge","commitsCount":11,"pusher":{"login":"andreaskurth","name":"Andreas Kurth","path":"/andreaskurth","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3583291?s=80&v=4"},"commit":{"message":"[kmac/doc] Improve documentation of `ERR_CODE` CSR\n\nSigned-off-by: Andreas Kurth ","shortMessageHtmlLink":"[kmac/doc] Improve documentation of ERR_CODE CSR"}},{"before":"0b78be64320fef404d43286c99183bb50da2da4e","after":"930c0cc9144c29c69a371bdb9c30ad33b5c42bf3","ref":"refs/heads/master","pushedAt":"2024-05-03T03:32:57.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"moidx","name":"moidx","path":"/moidx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/4177786?s=80&v=4"},"commit":{"message":"[rom_ext] Relax EDN0 configuration.\n\nThis change aims to mitigate some of the side effects caused by\nlowRISC/opentitan#22877.\n\n1. Increase the reseed interval in EDN0 to reduce the number of requests\n going to entropy_src.\n2. Increase the reseed interval in keymgr to reduce the number of\n requests going to edn0.\n\nBoth configuration values will be updated later on based on\nrecommendations derived from penetration testing and pre-silicon\nevaluation.\n\nSigned-off-by: Miguel Osorio ","shortMessageHtmlLink":"[rom_ext] Relax EDN0 configuration."}},{"before":"7f84f7cdb836718b7e2605fe628c537309bb527f","after":"0b78be64320fef404d43286c99183bb50da2da4e","ref":"refs/heads/master","pushedAt":"2024-05-02T22:32:19.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"pamaury","name":"Amaury Pouly","path":"/pamaury","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/121804?s=80&v=4"},"commit":{"message":"[rom_ext] temporarily disable cert updating\n\nThis temporarily disables DICE certificate updating in the ROM_EXT to\nunblock CI. A more permanent fix to #22921 will be rolled out shortly.\n\nSigned-off-by: Tim Trippel ","shortMessageHtmlLink":"[rom_ext] temporarily disable cert updating"}},{"before":"ecd9f08747a0211848e927aa352046608f61e226","after":"7f84f7cdb836718b7e2605fe628c537309bb527f","ref":"refs/heads/master","pushedAt":"2024-05-02T20:09:40.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"vogelpi","name":"Pirmin Vogel","path":"/vogelpi","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20307557?s=80&v=4"},"commit":{"message":"[csrng/rtl] Add reseed interval status error\n\nThis commit adds a new status error response, that is triggered\nwhenever the number of generates between reseeds exceeds the\nreseed_interval.\n\nSigned-off-by: Hakim Filali ","shortMessageHtmlLink":"[csrng/rtl] Add reseed interval status error"}},{"before":"7d9902c9badc36ebb36e0b4c1e5c32a4bd1ed71a","after":"7f3ce9509abf7965f21a86224813dde6b741ac74","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-02T16:35:19.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"cfrantz","name":null,"path":"/cfrantz","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/628742?s=80&v=4"},"commit":{"message":"[tock] Update Tock and its dependencies.\n\nThis updates the Tock kernel as far as possible without including a Rust toolchain update. This update includes a UART bug fix (https://github.com/tock/tock/pull/3927). I also updated `libtock-rs` and `tockloader` as well as updated the versions of their Cargo dependencies.\n\nSigned-off-by: Johnathan Van Why ","shortMessageHtmlLink":"[tock] Update Tock and its dependencies."}},{"before":"d5825270c74bdefbf9b653a9bdbaaed7c04efd04","after":"7d9902c9badc36ebb36e0b4c1e5c32a4bd1ed71a","ref":"refs/heads/earlgrey_es_sival","pushedAt":"2024-05-02T16:05:41.000Z","pushType":"pr_merge","commitsCount":4,"pusher":{"login":"engdoreis","name":"Douglas Reis","path":"/engdoreis","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/65042207?s=80&v=4"},"commit":{"message":"[dv, rstmgr] Increate dvsim timeout for alert_info test\n\nSigned-off-by: Douglas Reis ","shortMessageHtmlLink":"[dv, rstmgr] Increate dvsim timeout for alert_info test"}},{"before":"e012710b1ffb659a5e27655ead8a4f847b38a1ea","after":null,"ref":"refs/heads/backport-22904-to-master","pushedAt":"2024-05-02T14:35:45.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"a-will","name":"Alex Williams","path":"/a-will","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/782139?s=80&v=4"}},{"before":"3fe42548a074c3f7af8ca1e3c76afb09ef389c92","after":"ecd9f08747a0211848e927aa352046608f61e226","ref":"refs/heads/master","pushedAt":"2024-05-02T14:32:26.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jwnrt","name":"James Wainwright","path":"/jwnrt","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/105280833?s=80&v=4"},"commit":{"message":"[sival, i2c] Fix clock_stretching link in the testplan\n\nSigned-off-by: Douglas Reis \n(cherry picked from commit 739dcc321537441ea171ae8a1dac23dab7a7d135)","shortMessageHtmlLink":"[sival, i2c] Fix clock_stretching link in the testplan"}},{"before":"605da270ddcf70b2af5573e9524f9613bc89383d","after":"3fe42548a074c3f7af8ca1e3c76afb09ef389c92","ref":"refs/heads/master","pushedAt":"2024-05-02T14:23:08.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"vogelpi","name":"Pirmin Vogel","path":"/vogelpi","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20307557?s=80&v=4"},"commit":{"message":"[aes/sw] Load all-zero vector into PRNG buffer stage for masking off\n\nThe input masks are now taken from the PRNG buffer stage. This means\nafter loading the magic seed into the PRNG and having the PRNG output\nthe all-zero vector, the buffer stage needs to be updated as well.\nThis can be achieved by triggering via a clearing operation of the data\noutput registers.\n\nThis resolves lowRISC/OpenTitan#22917.\n\nSigned-off-by: Pirmin Vogel ","shortMessageHtmlLink":"[aes/sw] Load all-zero vector into PRNG buffer stage for masking off"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEQZ83SAA","startCursor":null,"endCursor":null}},"title":"Activity · lowRISC/opentitan"}