Running ibex-core dv env in questa

[imranjithkumar]

Would anyone happen to know how to run ibex-core tests in the Questa simulator? I would appreciate it if you could share your thoughts on how to run the ibex-core dv tests.

Thanks,
Ranjith

[rayamsumanth]

Hi
Currently there is an ongoing issue with Questasim. There is an active branch dedicated to questa sim simulations but it doesn't seem to work for some reason. I am also waiting to run it on Questa, though I tried with VCS and I was able to run the tests.

[imranjithkumar]

can you tell me how to run it with VCS? May be I can also try it.

[rayamsumanth]

There are README's under dv/uvm/core_ibex explaining the commands to run the tests. After installing the prerequisites (SPIKE, riscv-toolchain), you need to run the command command with the variations you like:

make --keep-going IBEX_CONFIG=opentitan SIMULATOR=vcs ISS=spike ITERATIONS=1 SEED=1 TEST=$TEST_NAME WAVES=0 COV=0

To start with, try running with the basic test listed in testlist.yaml:

make IBEX_CONFIG=opentitan SIMULATOR=vcs ISS=spike ITERATIONS=1 SEED=1 TEST=riscv_arithmetic_basic_test WAVES=0 COV=0

[imranjithkumar]

I am facing this kind of an error while trying to run.

I cannot install the ISS in my machine

[imranjithkumar]

Is xcelium is mandatory for running this env? did you meant synopsys vcs?

[rswarbrick]

The error that you've sent a screenshot about is not connected to your choice of simulator. The problem here is that pkgconfig doesn't know that riscv-riscv, riscv-disasm and riscv-fdt are installed on your machine. It might be that you need to install them! Or it might be that you need to set up PKG_CONFIG_PATH to tell it where to look.

[rayamsumanth]

Yes, I too initially faced this particular issue. The wrong step from my side was not setting $SPIKE_INSTALL_DIR. I rectified it by:

export SPIKE_INSTALL_DIR=/opt/spike-cosim

Then proceeded to install Spike simulator as shown here. Check for your spike installation and the paths you have given.

Check if you have the following directories in the spike installation path: bin, include, lib

[imranjithkumar]

Thanks @rayamsumanth for your input and it's very relevant.

With these instructions, we were able to overcome the issue and came up with the following error.

Kindly let me know how to proceed from here since I have no clue about this error.

[rswarbrick]

Hmm, that's not a great error message on our end (sorry). I've just looked at the Python and it's complaining that rtl_log didn't get substituted in the command (see the second-last line).

I think that this is being caused by the fact that the substitution is happening with a dictionary that doesn't have a definition with the key rtl_log for some reason. I don't think we've seen this happen locally, so I'm afraid you're going to have to do some debugging. I'd suggest adding print statements to figure out what's going on.

[rswarbrick]

@hcallahan-lowrisc: I think this code came from you in the first place. Would you mind taking a look and trying to work out what has come unstuck?

[A-B-S-Anik]

@imranjithkumar Are you able to run the flow with questa?

[hcallahan-lowrisc]

@imranjithkumar @A-B-S-Anik

#2096 should have fixed the error about parameters not being substituted in the riscvdv command. At this point, I cannot test further because I do not have access to questa. (I get the error No such file or directory: 'vmap')

Could you let me know if you get further?

make --keep-going IBEX_CONFIG=opentitan SIMULATOR=questa ISS=spike ITERATIONS=1 SEED=1 TEST=riscv_rand_instr_test WAVES=0 COV=0 VERBOSE=1

Thanks

[Mowneesh]

Hi Harry,

We have successfully generated the .S file from the RISCV-DV random instruction generator after making changes in the following files:

Many of the issues are related to simulator-oriented problems (SV/UVM syntax issues), while some pertain to the make-scripts. However, when attempting to convert the .S to .O file, we encountered a "cc1" error.

At this point, we are pausing this environment setup due to some internal tasks. We will resume this process later, and I will let you when we do.

Thanks.

[Mowneesh]

Hi,

We have successfully run a test in Questa. The attached document contains the number of errors and their corresponding fixes:
Running Ibex in Questasim - Errors & their corresponding fixes.pdf

We disabled the ISS Spike model for the test to pass. However, when we enable the model, we encounter the following error:

UVM_FATAL /home/edveon/Desktop/ibex_core/main/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2245653: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000000 but the DUT didn't report one at PC 80000080

Thanks.

[hcallahan-lowrisc]

Hi,

We have successfully run a test in Questa. The attached document contains the number of errors and their corresponding fixes: Running Ibex in Questasim - Errors & their corresponding fixes.pdf

We disabled the ISS Spike model for the test to pass. However, when we enable the model, we encounter the following error:

UVM_FATAL /home/edveon/Desktop/ibex_core/main/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2245653: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000000 but the DUT didn't report one at PC 80000080

Thanks.

Hey @Mowneesh, thanks for getting back to me and listing out all the errors you encountered.
Let me take a look at it all, and I'll come back to you when I have some ideas. Thanks