[dv] Improve instruction trace around faulting instructions

[GregAC]

When an executed instruction generates a fault we suppress its destination register write. On the RVFI interface this mean setting the write register index to 0. On the instruction trace this results in seeing x0 as the destination register, rather than the actual destination register. This can be confusing. We should improve our trace output to include the actual destination register in the printed instruction along with a note the write is suppressed due to a trap.

See lowRISC/opentitan#13134 for an example of this issue.