{"payload":{"header_redesign_enabled":false,"results":[{"id":"137416811","archived":false,"color":"#b2b7f8","followers":754,"has_funding_file":false,"hl_name":"lnis-uofu/OpenFPGA","hl_trunc_description":"An Open-source FPGA IP Generator","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":137416811,"name":"OpenFPGA","owner_id":62960593,"owner_login":"lnis-uofu","updated_at":"2024-05-29T21:36:58.853Z","has_issues":true}},"sponsorable":false,"topics":["fpga","fpga-soc"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":64,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Alnis-uofu%252FOpenFPGA%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/lnis-uofu/OpenFPGA/star":{"post":"1NQUT-mrOYXvweadSz6gcEnZWn5J_QzF6FH8VPj8o77os2aryLbxXLASI2YfXLIHz2sPqs0qwR2sKEfRekCsbQ"},"/lnis-uofu/OpenFPGA/unstar":{"post":"Sp9q9Z6QFZNCWb8Tl4UXuejZRtF4ufW3X7aSIuhACmNGPJMSu_Q8KHYfw2p5IBS2E-z7BX4hb8cxgBQD-IGVHA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"jgXwlRkcSY0P7iMGbnZaz0cx6mAOPEpbKsH9d-tOTLetaNMj29Z_AMSe0uJ-7EP_7nllSQwdkgRXfw4YW7XS0g"}}},"title":"Repository search results"}