Improve stack handling for RISC-V Machine outliner

[ilovepi]

This is a work item identified in the gap analysis done in #89822.

Stack frame handling, seems to be much more involved in the Arm outliners, with many routines and heuristics trying to optimize and maximize outlining opportunities.

First, there are several routines dealing w/ both stack transformations and analysis to help identify outlining candidates and in some cases fix up the outlining call site (e.g. copying from 1 register to another or adjusting offsets after outlining). Some of these tasks, like fixing up offsets are already handled for RISC-V or in the generic CodeGen bits. However, ARM targets do significantly more, and do more to ensure the outlined calls can be tail-called whenever possible.

I'll follow up w/ more details soon, after a more thorogh review of what is required for RISC-V.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Paul Kirth (ilovepi)

This is a work item identified in the gap analysis done in https://github.com//issues/89822.

Stack frame handling, seems to be much more involved in the Arm outliners, with many routines and heuristics trying to optimize and maximize outlining opportunities.

First, there are several routines dealing w/ both stack transformations and analysis to help identify outlining candidates and in some cases fix up the outlining call site (e.g. copying from 1 register to another or adjusting offsets after outlining). Some of these tasks, like fixing up offsets are already handled for RISC-V or in the generic CodeGen bits. However, ARM targets do significantly more, and do more to ensure the outlined calls can be tail-called whenever possible.

I'll follow up w/ more details soon, after a more thorogh review of what is required for RISC-V.