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Kernel error with dma size of 65 KB #13

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ericqui opened this issue Jul 3, 2018 · 2 comments
Open

Kernel error with dma size of 65 KB #13

ericqui opened this issue Jul 3, 2018 · 2 comments

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@ericqui
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ericqui commented Jul 3, 2018

I've been using 32 KB dma transactions to reliably transfer streaming data. I can read 1 or 100,000 dma dma blocks reliable. However, when increasing the read size by a factor of 2 (to 65KB), I get a kernel error:

[ 3052.666641] xilinx-vdma 40450000.axidma: Channel de8e5810 has errors 200, cdr 780 tdr 1f502900
[ 3053.667960] xilinx-vdma 40450000.axidma: Cannot start channel de8e5810: 10209

It appears that the error is sourced somewhere in the xilinx dma driver. When this happens, the dma also hangs, never returning (data continues streaming, though now it is just dropped in the fpga fabric buffering). I have two 128 KB FIFOs going into the DMA so it isn't that I'm overrunning those. Do you have any ideas of what can be done to increase the dma size?

@jeremytrimble
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jeremytrimble commented Jul 3, 2018

I can't be sure but I've seen this sort of thing happen before if your AXI DMA core was configured with a "Width of Buffer Length" register that is too small.

Representing 32*1024 requires at least a 16 bit register. Going up to 64*1024 requires a 17-bit register, but if your AXI DMA was configured for 16 bits then the high-order bits will get truncated and DMA will just see a zero in the buffer length field of your descriptor and that will cause the DMA core to return an error (I think), or maybe just hang.

Have a look at: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf, page 76.

Hope this helps!

@ericqui
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ericqui commented Jul 3, 2018

That makes sense. I've actually already maximized my buffer length to 23 bits. My address width is 32 bits, all data widths are 32 bits and my max burst size is 256.

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