{"payload":{"header_redesign_enabled":false,"results":[{"id":"753164038","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"jElhamm/Verilog-HDL-Codes-Collection","hl_trunc_description":"\"Repository containing a collection of Verilog code modules and test bench for digital design projects. \"","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":753164038,"name":"Verilog-HDL-Codes-Collection","owner_id":124600456,"owner_login":"jElhamm","updated_at":"2024-04-01T19:41:32.489Z","has_issues":true}},"sponsorable":false,"topics":["counter","encoder","decoder","verilog","alu","multiplexer","comparator","testbench","verilog-hdl","gates","7segment","shiftregister","verilog-programs","verilog-simulator","verilog-project","testbench-generator-verilog"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":49,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AjElhamm%252FVerilog-HDL-Codes-Collection%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/jElhamm/Verilog-HDL-Codes-Collection/star":{"post":"VEN8u9IxQQf_A9u8_18oKJFfsh2gA2qO0qdbyZp4tC-o9pFc5DY9gv8LuIGOpTyuAYYLKb6uG5ug0l0NV8GUmw"},"/jElhamm/Verilog-HDL-Codes-Collection/unstar":{"post":"sBbpHvwMJ1JIR14TB9JUco1zHC6SSmKLlARCHRAueeT7u_BlPS9BE4GP3F68tnwHbx53gEGuruu__G5nHqFwFA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"HxlJd1aQIV1KOlRwjY4cShOQGum7SFtxsgsUwe-urFF0V1umHLQLpOqYyMyRZJaXTJn0Fh9u9Y2vdbeXgMfRLg"}}},"title":"Repository search results"}