{"payload":{"header_redesign_enabled":false,"results":[{"id":"241934964","archived":false,"color":"#DAE1C2","followers":0,"has_funding_file":false,"hl_name":"isikozsoy/CS223_Course_Project","hl_trunc_description":"The aim of this project is to learn how to use the 7 segment module, how to give input via switches on Basys 3 FPGA Board, how to use the…","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":241934964,"name":"CS223_Course_Project","owner_id":47677255,"owner_login":"isikozsoy","updated_at":"2020-02-20T16:53:38.286Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":69,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aisikozsoy%252FCS223_Course_Project%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/isikozsoy/CS223_Course_Project/star":{"post":"l9MHP_rzNXKw2SnEuAuca0CCJMHIYAikRDcbdTTY9I-oZFSC5RsVekLf2v6gFUWFHo0xaBUOSCBCtb-CitOaQw"},"/isikozsoy/CS223_Course_Project/unstar":{"post":"B8f62fmw6ojQFKOSlfAPQLM3heBn9X6Ju0qO88ibDYYC3xkuqCjU72OcoOnB-l7DSbvGVdLuUdy0cUZ9setnGw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"G5qO7odD8bats7pF-Ax-4zNHhF0sCGi2Khfk0Bz6CARWX8S9zsQGW9vW0JKeQ6-QICog46NvLIBUj3nN4mWO5Q"}}},"title":"Repository search results"}