{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":75980044,"defaultBranch":"main","name":"xed","ownerLogin":"intelxed","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2016-12-08T22:21:22.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/24464627?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1712166910.0","currentOid":""},"activityList":{"items":[{"before":"d08a6f66f780a685f26322960cd3ae297dbad931","after":"6d87b5481aa53b5ab1fc2b5a5622759c46746bf9","ref":"refs/heads/main","pushedAt":"2024-04-03T17:55:08.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"sdeadmin","name":null,"path":"/sdeadmin","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/94464062?s=80&v=4"},"commit":{"message":"External Release v2024.04.01\n\nThis release updates XED according to Intel's latest APX spec (Rev-04), April 2024.\r\nIt includes:\r\n  - Remove promoted SHA and KeyLocker EVEX instructions\r\n  - Encoding update for URDMSR/UWRMSR\r\n  - Addition of missing CPUID sensitivity for promoted POPCNT EVEX instruction\r\n  - Update the handling of EVEX.U and reinterpretation to X4\r\n\r\n\r\nGeneral:\r\n  - Enable a secured build using a new `--security-level` mfile.py knob (1->Medium, 2->High, 3->Highest).\r\n    The default level is 1 (will be raised to 2 in a future release)\r\n    Please expect performance degradation with level 3.\r\n  - Drop the ICC/ICL build options using mfile.py\r\n\r\nAdd:\r\n  - AMX: Support the restriction of illegal register combination (Solves intelxed/xed#303)\r\n  - Disassembler: Print sequential registers using \"+(N-1)\" notation\r\n  - Add ENC2 support for Intel APX architecture (TBD: REX2 for EGPR support)\r\n  - Add ENC2 support for KOP instructions\r\n\r\nFix:\r\n  - ISA definition fixes (APX/MOVDIR64B missing operands, Fix CPUID for SYS{ENTER,EXIT}, fix MMX extensions)\r\n  - RFLAGS: Fix width definition and wrong duplicated operands for several instructions (Solves intelxed/xed#320)\r\n  - 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The XED user guide was updated with explanations for APX, AVX10, and more (https://intelxed.github.io/)\r\n  - Updated Python version requirement and documentation to 3.8 (closes intelxed/xed#306)\r\n\r\nAdded:\r\n  - Added new APX promoted instructions: RAO-INT and USER-MSR (APX Arch Spec Rev-03)\r\n  - Added a complete XED encoder support for Intel APX architecture\r\n  - APX(CCMPcc/CTESTcc): Added operand parser API that extracts the default-flags-values from XED DFV pseudo-register\r\n  - Updated APX CPUID sensitivity with additional Legacy/VEX CPUID records\r\n  - FRED: Added compatibility mode SYSCALL\r\n\r\nFixed:\r\n  - Fixed missing REX2 prefix restriction for several legacy instructions\r\n  - APX/JMPABS: Added missing RIP suppressed operand\r\n  - ENC2: Fixed the encoding of instruction's operands\r\n  - Fixed CPUID records for KEYLOCKER and MOVDIR instructions\r\n  \r\nModified:\r\n  - Updated AVX10 CPUID sensitivity of 64-bit KMASK instructions (AVX10 Arch Spec Rev-02)\r\n  - Improved Python code for genutil.py (resolves intelxed/xed#307)\r\n\r\nCo-authored-by: marjevan <marjevan@users.noreply.github.com>","shortMessageHtmlLink":"External Release v2023.12.19"}},{"before":"01a6da8090af84cd52f6c1070377ae6e885b078f","after":"d7d46c73fb04a1742e99c9382a4acb4ed07ae272","ref":"refs/heads/main","pushedAt":"2023-10-16T12:00:28.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"sdeadmin","name":null,"path":"/sdeadmin","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/94464062?s=80&v=4"},"commit":{"message":"External Release v2023.10.11\n\nUpdated CPUs and instructions according to ISE (Intel&reg; Architecture \r\nInstruction Set Extensions and Future Features) rev-050, September 2023.\r\n\r\nAdded:\r\n  - New USER_MSR and FRED instructions\r\n  - New chips: Emerald Rapids, Clearwater Forest and Panther Lake\r\n  - ENC2 updates with support for AMX/EVEX, IMM dest operand and EVEX \r\n    scalable operand size instructions\r\n  - Instructions for contributing to the Intel&reg; XED project (README.md)\r\n\r\nFixed:\r\n  - xed_agen() API: Avoid potential signed integer overflow (closes intelxed/xed#305)\r\n  - AMX: Fixed element types and updated extension definition\r\n  \r\nModified:\r\n  - Updated DAZ behavior of several AVX_NE_CONVERT instructions\r\n  - Dropped Grand Ridge (No new ISA over SRF)\r\n  - Updated PBNDKB CPUID name\r\n\r\n\r\nCo-authored-by: marjevan <marjevan@users.noreply.github.com>","shortMessageHtmlLink":"External Release v2023.10.11"}},{"before":"df2b089d0d9be82f8f9d26ca761f06ac0752e48f","after":null,"ref":"refs/tags/v2023.08.21","pushedAt":"2023-08-21T17:46:56.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"marjevan","name":"Maor Arjevani","path":"/marjevan","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/87116213?s=80&v=4"}},{"before":"539a6a349cf7538a182ed3ee1f48bb9317eb185f","after":"01a6da8090af84cd52f6c1070377ae6e885b078f","ref":"refs/heads/main","pushedAt":"2023-08-21T17:19:57.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"sdeadmin","name":null,"path":"/sdeadmin","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/94464062?s=80&v=4"},"commit":{"message":"External Release v2023.08.21\n\nThis release adds support for Intel® APX (Advanced Performance Extensions) and AVX10 \r\n(Advanced Vector Extensions 10) according to the August 2023 latest specification revisions.\r\nThe complete documentation can be found on Intel's official SDM webpage.\r\n\r\n\r\n### APX Support:\r\n  Intel® Advanced Performance Extensions (APX) expands the Intel 64 instruction set architecture with\r\n  access to more registers and adds various new features that improve general-purpose performance.\r\n  \r\n  The external release:\r\n  - Adds a complete decoder support. Including REX2 prefix, Promoted-To-EVEX instructions and new instructions\r\n  - Adds a complete chip-check support\r\n  - Adds a partial encoder support\r\n  - For a complete support description and status, please check: datafiles/apx-f/README.md\r\n  - Decoder usage examples can be found in xed-ex1.c example tool\r\n\r\n\r\n### AVX10 Support:\r\nIntel® Advanced Vector Extensions 10 (Intel® AVX10) represents the first major new vector ISA since the introduction \r\nof Intel® Advanced Vector Extensions 512 (Intel® AVX-512) in 2013. This ISA will establish a common,\r\nconverged vector instruction set across all Intel architectures, incorporating the modern vectorization aspects of\r\nIntel AVX-512. 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