{"payload":{"header_redesign_enabled":false,"results":[{"id":"135932086","archived":false,"color":"#b2b7f8","followers":67,"has_funding_file":false,"hl_name":"hell03end/verilog-uart","hl_trunc_description":"Simple 8-bit UART realization on Verilog HDL.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":135932086,"name":"verilog-uart","owner_id":13778220,"owner_login":"hell03end","updated_at":"2024-04-27T16:48:04.012Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","uart","hdl","quartus"],"type":"Public","help_wanted_issues_count":2,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":93,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ahell03end%252Fverilog-uart%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/hell03end/verilog-uart/star":{"post":"uU6Vto073YSrOf-Br2yuWsCXs1B1zkuY0kS8PN6jN78eA3FfcPDVMTd-bZTk3xPx5qBYDKYah5ePBNsBtZHteQ"},"/hell03end/verilog-uart/unstar":{"post":"MbDYbzeUXt88oxJkmBBmtl8IFnrhvnjyD9tHwJQgrwXj5Yic2lIpdJYBm64OMGU8nfREY_NbKS2Id1nnntAwUg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"syo5y-H53VKIGY7wEPM1p_WgltNXjfIz4YL7YF3drjxfF955whNLnotHqi4j9axyO5mwJ5_YyNQm-_DKdFmEvw"}}},"title":"Repository search results"}