AVX version of the SSE routines

[maximmasiutin]

Our application uses AVX (VEX-prefixed) instructions. As you know, transition between SSE instructions that don’t have VEX prefix and VEX-prefixed AVX instructions involves huge state transition penalty. You may find more information at https://software.intel.com/en-us/articles/avoiding-avx-sse-transition-penalties

The VZEROUPPER, which is supposed to help avoid transition penalty, is very expensive (slow) on some processors, and there is no reliable way on how to detect whether it is expensive or cheap. Besides that, contrary to the logic, testing shows that on Kaby Lake processors, calling VZEROUPPER at least once in an application makes subsequent non-VEX-prefixed SSE instructions 25% slower.
So, the most reliable way to avoid the penalties that slow down the application is is just to avoid AVX-SSE transitions – for example, by prefixing all the instructions with the VEX prefix. So, all instructions will become vector and there will be no transitions and no need to call VZEROUPPER.
To accomplish that, we should detect if our CPU supports AVX, and, if it does, never call a single non-VEX-prefixed SSE instruction.

Please consider adding VEX code as an alternative for SSE code for 64-bit version of Graphics32.
Unfortunately, Delphi internal assembler doesn’t yet support AVX instructions, so I’ve put byte codes.
You can also put bytecodes, by ending instructions in another compiler.

I can help you with the implementation if you wish.

[maximmasiutin]

Besides that, AVX provides 256-bit YMM registers, and there have been released processors to the market that support AVX-512 with ZMM registers, which are really cool! We may think on how can we use these features for the Graphics32 library. The AVX-512 instructions are available on Skylake-X Core i7 and i9 models, which are quite affordable, as well as on more expensive Intel's Xeon Phi x200 (Knights Landing), which was released more than a year ago.

[CWBudde]

At the moment I see at least two scenarios about how to include support for AVX.

Either some contributor does the adaptions in a fork (I'm willing to review and accept the pull request if it's proven to work reliable) or someone sponsors the development (to buy a recent computer with AVX-512 to get this included as well).

As far as I can see it the changes might take about 1-2 weeks of work, especially if it should get tested in many scenarios (especially older compilers, older computers etc.). In particular since AVX-512 <> AVX-512 nowadays (the supported features vary from processor to processor) it can get tricky to support all possible combinations.

[maximmasiutin]

We have managed to get an i9 processor to test the AVX-512 instructions.

The AVX-512 is relatively new and, probably, in future, will be equipped only on most expensive processors.

As about AVX, it is more or less ubiquitous, equipped on all Intel processors except the cheapest Celeron and Pentium.

As about the different kinds, there are mostly 3 kinds of instructions:

1. AVX
2. AVX2
3. AVX-512

As about the differences between AVX and AVX2 - they are not that significant. Mainly, processors that only have AVX but not AVX2 require an 'vzeroupper' instruction before and after AVX code, since Delphi uses legacy SSE, especially under 64-bit, and without 'vzeroupper' there will be huge transition penalties.

AVX-2 and AVX-512, to the contrary, don't have such huge penalties, and 'vzeroupper' is not neede or may even slow things down.

[maximmasiutin]

It's better to use NASM, not the built-in Delphi assembler since it doesn't support AVX. I've done, for example, AVX, AVX2 and AVX-512 support in NASM for a FastMM4 fork: https://github.com/maximmasiutin/FastMM4-AVX