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Describe the bug
As reported in one of the gem5 slack channels (https://gem5-workspace.slack.com/archives/C03K26BGTKL/p1703584762742109) the queued prefetcher translates request with the BaseMMU::Read argument 1.
This automatically informs the MMU to look into the D-TLB 2 and it works ok for D-side prefetchers.
This is not the case for I-side ones.
In that scenario, the D-TLB lookup will likely miss and (unless there is a second level TLB) will request the translation though the page table walker. This means:
Unnecessary PTW affecting prefetch timing
Increased simulation time.
I believe the solution would be to tag a prefetcher accordingly so that either BaseMMU::Read or BaseMMU::Execute will be used.
Host Operating System
All
Host ISA
All
The text was updated successfully, but these errors were encountered:
Describe the bug
As reported in one of the gem5 slack channels (https://gem5-workspace.slack.com/archives/C03K26BGTKL/p1703584762742109) the queued prefetcher translates request with the BaseMMU::Read argument 1.
This automatically informs the MMU to look into the D-TLB 2 and it works ok for D-side prefetchers.
This is not the case for I-side ones.
In that scenario, the D-TLB lookup will likely miss and (unless there is a second level TLB) will request the translation though the page table walker. This means:
I believe the solution would be to tag a prefetcher accordingly so that either BaseMMU::Read or BaseMMU::Execute will be used.
Host Operating System
All
Host ISA
All
The text was updated successfully, but these errors were encountered: